1. Programmable Logic Devices Zainalabedin Samadi

2. Embedded Systems Technology  Programmable Processors  Application Specific Processor (ASIP)  Single purpose hardware 2

3. Embedded System Technology  Differ in their customization for the problem at hand 3 total = 0 for i = 1 to N loop total += M[i] end loop General-purpose processor Single-purpose hardware Application-specific processor Desired functionality

4. General-purpose processors  Programmable device used in a variety of applications  Also known as “microprocessor”  Features  Program memory  General datapath with large register file and general ALU  User benefits  Low time-to-market and NRE costs  High flexibility  Example: Pentium, ARM, … 4 IRPC Register file General ALU DatapathController Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory

5. NRE and unit cost metrics  Unit cost  the monetary cost of manufacturing each copy of the system, excluding NRE cost  NRE cost (Non-Recurring Engineering cost)  The one-time monetary cost of designing the system  total cost = NRE cost + unit cost * # of units  per-product cost = total cost / # of units = (NRE cost / # of units) + unit cost 5

6. Application-specific processors  Programmable processor optimized for a particular class of applications having common characteristics  Features  Program memory  Optimized datapath  Special functional units  Benefits  Some flexibility, good performance, size and power  Example: DSP, Media Processor 6 IRPC Registers Custom ALU DatapathController Program memory Assembly code for: total = 0 for i =1 to … Control logic and State register Data memory

7. Single-purpose hardware  Digital circuit designed to execute exactly one program  coprocessor, accelerator  Features  Contains components needed to execute a single program  No program memory  Benefits  Fast  Low power  Small size 7 Datapath Controller Control logic State register Data memory index total +

8. IC technology  Three types of IC technologies  Full-custom/VLSI  Semi-custom ASIC (gate array and standard cell)  PLD (Programmable Logic Device) 8

9. Full-custom/VLSI  All layers are optimized for an embedded system’s particular digital implementation  Placing transistors  Sizing transistors  Routing wires  Benefits  Excellent performance, small size, low power  Drawbacks  High NRE cost (e.g., $300k), long time-to-market 9

10. Semi-custom  Lower layers are fully or partially built  Designers are left with routing of wires and maybe placing some blocks  Benefits  Good performance, good size, less NRE cost than a full- custom implementation (perhaps $10k to $100k)  Drawbacks  Still require weeks to months to develop 10

11. PLD (Programmable Logic Device)  All layers already exist  Designers can purchase an IC  Connections on the IC are either created or destroyed to implement desired functionality  Field-Programmable Gate Array (FPGA) very popular  Benefits  Low NRE costs, almost instant IC availability  Drawbacks  Bigger, expensive (perhaps $30 per unit), power hungry, slower 11

12. Comparison 12 TechnologyPerformance/ Cost Time until running Time to change code functionality ASICVery HighVery LongImpossible FPGAMedium ASIP/ DSP HighLong GenericLow-MediumVery Short Very Short Speed Flexibility

13. 13

14. 14

15. Roadmap  PROM  PLA  PAL  CPLD  FPGA 15

16. PLD Definition  Programmable Logic Device (PLD):  An integrated circuit chip that can be configured by end use to implement different digital hardware  Also known as “Field Programmable Logic Device (FPLD) “ 16

17. PLD Advantages  Short design time  Less expensive at low volume 17 Volume Cost Nonrecurring engineering cost PLD ASIC

18. PLD Categorization 18 PLD SPLD HCPLD FPGACPLD PLAPAL Simple PLD High Capacity PLD Programmable Logic Array Programmable Array Logic Complex PLD Field Programmable Gate Array

19. Programmable ROM (PROM) 19 2 N x M ROM N inputM output Address: N bits; Output word: M bits ROM contains 2 N words of M bits each The input bits decide the particular word that becomes available on output lines

20. Logic Diagram of 8x3 PROM 20 Sum of minterms

21. Combinational Circuit Implementation using PROM 21 000100 001010 010011 011100 100010 101001 110100 111010 I0 I1 I2 F0 F1 F2 F0 F1 F2

22. PROM Types  Programmable PROM  Break links through current pulses  Write once, Read multiple times  Erasable PROM (EPROM)  Program with ultraviolet light  Write multiple times, Read multiple times  Electrically Erasable PROM (EEPROM)/ Flash Memory  Program with electrical signal  Write multiple times, Read multiple times 22

23. PROM: Advantages and Disadvantages  Widely used to implement functions with large number of inputs and outputs  Design of control units (Micro-programmed control units)  For combinational circuits with lots of don’t care terms, PROM is a wastage of logic resources 23

24. CPLD 24 Logic Block Logic Block Logic Block Logic Block I/O Programmable Interconnect

25. CPLD Logic Block  Simple PLD  Inputs  Product-term array  Product term allocation function  Macro-cells (registers)  Logic blocks executes sum-of-product expressions and stores the results in micro- cell registers  Programmable interconnects route signals to and from logic blocks 25

26. Major CPLD Resources  Number of macro-cells per logic block  Number of inputs from programmable interconnect to logic block  Number of product terms in logic block 26

27. Structure of FPGA (Xilinx) 27 Logic Block I/O Block Interconnect

29. 29

30. 30

31. Configurable Logic Block CLB 31

32. Block RAM Xilinx FPGAs - 32

33. Details of One Virtex Slice Xilinx FPGAs - 33

34. Implements any Two 4-input Functions Xilinx FPGAs - 34 4-input function 3-input function; registere d

35. Implements any 5-input Function Xilinx FPGAs - 35 5-input function

36. Logic Function  Implemented as look-up table (LUT)  K-input LUT corresponds to 2 K x 1 bit memory  K-input LUT can implement any k-input 1-output logic function 36

37. Configuring FPGA  Configure CLB and IOB  Configure interconnect  Interconnect technology  SRAM  Anti-fuse (program once)  EPROM / EEPROM 37

38. Programming Technology NameRe-programmableVolatile EPROMyes (out of circuit)no EEPROMyes (in circuit)no SRAMyes (in circuit)yes Antifuseno 38

39. PLD Logic Capacity  SPLD: about 200 gates  CPLD  Altera FLEX (250K logic gates)  Xilinx XC9500  FPGA  Xilinx Vertex-E ( 3 million logic gates)  Xilinx Spartan (10K logic gates)  Altera 39

40. FPGA Design Flow 40 Design Entry Design Implementation Design Verification FPGA Configuration

41. Computer-aided Design  Can't design FPGAs by hand  way too much logic to manage, hard to make changes  Hardware description languages  specify functionality of logic at a high level  Validation - high-level simulation to catch specification errors  verify pin-outs and connections to other system components  low-level to verify mapping and check performance  Logic synthesis  process of compiling HDL program into logic gates and flip-flops  Technology mapping  map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs) Xilinx FPGAs - 41

42. CAD Tool Path (cont’d)  Placement and routing  assign logic blocks to functions  make wiring connections  Timing analysis - verify paths  determine delays as routed  look at critical paths and ways to improve  Partitioning and constraining  if design does not fit or is unroutable as placed split into multiple chips  if design it too slow prioritize critical paths, fix placement of cells, etc.  few tools to help with these tasks exist today  Generate programming files - bits to be loaded into chip for configuration Xilinx FPGAs - 42

43. Design Entry (DK1 in our case) 43 SchematicHDL Compile Logic Equations Minimize Reduced Logic Equations (Netlist) Test vectors Simulation

44. Design Implementation  Input: Netlist Output: bitstream  Map the design onto FPGA resources  Break up the circuit so that each block has maximum n inputs  NP-hard problem  However, optimal solution is not required 44

45. Design Implementation (Cont.)  Place: assigns logic blocks created during mapping process to specific location on FPGA  Goal: minimize length of wires  Again NP-hard  Route: routes interconnect paths between logic blocks  NP-hard 45

46. Design Implementation Techniques  Simulated annealing  Genetic algorithm  Mincut method  Heuristic method 46

47. Design Verification & FPGA Configuration  Functional Simulation  Timing Simulation  Download bitstream into FPGA 47