Spring 2002EECS150 - Lec12-cl3 Page 1 EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3 March 4, 2002 John Wawrzynek.

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Spring 2002EECS150 - Lec12-cl3 Page 1 EECS150 - Digital Design Lecture 12 - Combinational Logic Circuits Part 3 March 4, 2002 John Wawrzynek

Spring 2002EECS150 - Lec12-cl3 Page 2 In the News...

Spring 2002EECS150 - Lec12-cl3 Page 3 Multiplication a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier Xa 3 b 0 a 2 b 0 a 1 b 0 a 0 b 0 a 3 b 1 a 2 b 1 a 1 b 1 a 0 b 1 Partial a 3 b 2 a 2 b 2 a 1 b 2 a 0 b 2 products a 3 b 3 a 2 b 3 a 1 b 3 a 0 b 3... a 1 b 0 +a 0 b 1 a 0 b 0 Product Many different circuits exist for multiplication. Each one has a different balance between speed (performance) and amount of logic (cost).

Spring 2002EECS150 - Lec12-cl3 Page 4 “Shift and Add” Multiplier Sums each partial product, one at a time. In binary, each partial product is shifted versions of A or 0. Control Algorithm: 1. P  0, A  multiplicand, B  multiplier 2. If LSB of B==1 then add A to P else add 0 3. Shift [P][B] right 1 4. Repeat steps 2 and 3 n-1 times. 5. [P][B] has product. Cost  n,  = n clock cycles. What is the critical path for determining the min clock period?

Spring 2002EECS150 - Lec12-cl3 Page 5 “Shift and Add” Multiplier Signed Multiplication: Remember for 2’s complement numbers MSB has negative weight: ex: -6 = = = = -6 Therefore for multiplication: a) subtract final partial product b) sign-extend partial products Modifications to shift & add circuit: a) adder/subtractor b) sign-extender on P shifter register

Spring 2002EECS150 - Lec12-cl3 Page 6 Array Multiplier Generates all partial products simultaneously. Each row: n-bit adder with AND gates. What is the critical path? Delay  ?, cost  ?

Spring 2002EECS150 - Lec12-cl3 Page 7 Carry-save Addition Speeding up multiplication is a matter of speeding up the summing of the partial products. “Carry-save” addition can help. Carry-save addition passes (saves) the carries to the output, rather than propagating them. Example: sum three numbers, 3 10 = 0011, 2 10 = 0010, 3 10 = c 0100 = 4 10 s 0001 = c 0010 = 2 10 s 0110 = = 8 10 carry-save add carry-propagate add In general, carry-save addition takes in 3 numbers and produces 2. Whereas, carry-propagate takes 2 and produces 1. With this technique, we can avoid carry propagation until final addition

Spring 2002EECS150 - Lec12-cl3 Page 8

Spring 2002EECS150 - Lec12-cl3 Page 9 Array Multiplier with Carry-Save

Spring 2002EECS150 - Lec12-cl3 Page 10

Spring 2002EECS150 - Lec12-cl3 Page 11

Spring 2002EECS150 - Lec12-cl3 Page 12 CL Circuits from Mano Magnitude Comparator Multiplexors (revisited) Decoders –basic –hierarchical Encoders –standard –Priority Encoder

Spring 2002EECS150 - Lec12-cl3 Page 13 Magnitude Comparator We studied magnitude comparators in CS61c as part of the MIPS processor design. What was that method? Why that then and not now? (A>B) = A 3 B’ 3 + x 3 A 2 B’ 2 + x 3 x 2 A 1 B’ 1 + x 3 x 2 x 1 A 0 B’ 0 (A=B) = x 3 x 2 x 1 x 0 (A>B) = A’ 3 B 3 + x 3 A’ 2 B 2 + x 3 x 2 A’ 1 B 1 + x 3 x 2 x 1 A’ 0 B 0

Spring 2002EECS150 - Lec12-cl3 Page 14 Multiplexors Revisited Basic AND/OR form NAND/NAND tristate buffer based transmission gate based hierarchical decoder based –delay analysis

Spring 2002EECS150 - Lec12-cl3 Page 15 Decoders

Spring 2002EECS150 - Lec12-cl3 Page 16 Hierarchical Decoders

Spring 2002EECS150 - Lec12-cl3 Page 17 Encoders Generates binary code at output corresponding to input code. Example: one-hot to binary encoder. (Opposite of decoder) a b c d x y Priority Encoder: –If two or more inputs are equal to 1 at the same time the input with the highest “priority” will take precedence. Example: a b c d x y V “V” is the valid signal, “d” has highest priority.