1. Combinational Circuitsby
Dr. Amin Danial Asham

2. References
Digital Design 5th Edition, Morris Mano

3. DESIGN PROCEDURE (continue)
Adder (continue)
Binary adder
The binary adder is a digital combinational circuit that perform arithmetic summation for two binary numbers.
A binary adder can be implemented using cascaded full adders with the output carry of a full adder is connected to the input carry of the next full adder.
A four bit binary ripple adder can be constructed from 4 full adders as shown.
The bits of binary number A and binary number B are designated by subscript numbers starting from right to left with the subscript 0 for the least significant bit.
Carries are connected in a chain through the adders. The input C0 propagate through the adders to the output carry C4

4. DESIGN PROCEDURE (continue) Adder (continue)
Binary adder (continue)
As in any combinational circuit the signal must propagate through the gates before the correct output is available in the output terminals.
The total propagation time is equal to the propagation delay of a typical gate, times the number of gate levels in the circuit.
The longest propagation delay time in an adder is the time it takes the carry to propagate through the full adders. For example:
Inputs A3 and B3 are available as soon as input signals are applied to the adder.
However, input carry C3 does not settle to its find value until C2 is available from the previous stage. Similarly, C2 has to wait for C1 and so on down to C0.
Thus, only after the carry propagates and ripples through all stages will the last output S3 and carry C4 settle to their final correct value.

5. DESIGN PROCEDURE (continue) Adder (continue) Binary adder (continue)
Form the following full adder circuit diagram we find:
The signals 𝑃 𝑖 and 𝐺 𝑖 settle to their steady state values after their propagation through their respective gates. These two signals depend only on the input signals 𝐴 𝑖 and 𝐵 𝑖 which may be applied to all stages simultaneously.
The signal from the input 𝐶 𝑖 to the output signal 𝐶 𝑖+1 propagate through an AND and an OR gates, which constitute two gate levels.
Therefore, if there is 4 full adder stages the output carry 𝐶 4 would have 2×4=8 gate levels from 𝐶 0 to 𝐶 4 .
Similarly, for n-bit adder the carry signal propagates through 2n gate levels.
The carry propagation delay is very important since it limits the speed of an adder.

6. DESIGN PROCEDURE (continue)
Adder (continue)
Binary adder (continue)
𝑃 𝑖 = 𝐴 𝑖 ⨁ 𝐵 𝑖
𝑆 𝑖 = 𝑃 𝑖 ⨁ 𝐶 𝑖
Therefore,
𝐶 1 = 𝑃 0 𝐶 0 + 𝐺 0
𝐶 2 = 𝑃 1 𝐶 1 + 𝐺 1 = 𝑃 1 𝑃 0 𝐶 0 + 𝑃 1 𝐺 0 + 𝐺 1
𝐶 3 = 𝑃 2 𝐶 2 + 𝐺 2 = 𝑃 2 𝑃 1 𝑃 0 𝐶 0 + 𝑃 2 𝑃 1 𝐺 0 + 𝑃 2 𝐺 1 + 𝐺 2
In the same way 𝐶 4 can be driven.
As shown, the Boolean functions of the carries are sum of products which can be implemented by only two level gates in parallel for all carries and hence 𝐶 𝑖+1 does not have to wait for the previous carries. This circuit is called Carry Lookahead Generator.
𝐺 𝑖 = 𝐴 𝑖 𝐵 𝑖
𝐶 𝑖+1 = 𝑃 𝑖 𝐶 𝑖 + 𝐺 𝑖

7. DESIGN PROCEDURE (continue)
Adder (continue)
Binary adder (continue)

8. DESIGN PROCEDURE (continue)
Adder (continue)
Binary adder (continue)
From The construction of a four-bit adder with a carry lookahead generator we find that :
Each sum output requires two exclusive-OR gates.
The output of the first exclusive-OR gate generates the 𝑃 𝑖 variable, and the AND gate generates the 𝐺 𝑖 variable. The carries are propagated through the carry lookahead generator and applied as inputs to the second exclusive-OR gate.
All output carries are generated after a delay through two levels of gates. Thus, outputs 𝑆 𝑖 ’s have equal propagation delay times.

9. DESIGN PROCEDURE (continue) Binary Adder -Subtractor
To calculate the subtraction A-B, the 2’s complement of B is added to A.
The 2’s complement of B can be obtained from the 1’s complement of B adding 1.
Noting that the 1’s complement of binary digit 𝐵 𝑖 ′= 𝐵 𝑖 ⨁1.
Therefore the subtractor can be built using binary adder as shown in the following figure, where 𝑀=1 to get the 1’s complement of B and convert it to 2’s complement by adding input carry 𝐶 0 =𝑀=1.
In case of 𝑀=0, the circuit acts as normal binary adder.
4-bit Adder-Subtractor

10. DESIGN PROCEDURE (continue) Binary Adder –Subtractor (continue)
Overflow occurs in two n-bits numbers are added and the result needs n+1 bits.
This case occurs if two positive or two negative numbers are added. Whereas no overflow occur if positive number is added to negative number since the result is smaller in magnitude than the larger of the original numbers.
In the next example adding two positive or negative 8-bits numbers where the 8th bit is the sign, the sum is 9-bits number where the 9th bit is the correct sign bit.
From the former example an overflow is detected by checking the carry into the sign bit and carry out from the sign bit, if they are not equal then there is an overflow.
This method of detection is valid in case of 2’complement.

11. DESIGN PROCEDURE (continue)
Binary Adder –Subtractor (continue)
Therefore, in case of unsigned in the adder-subtractor circuit, if the added numbers are considered unsigned C is the carry out after addition operation or the borrow after subtraction.
In case of signed numbers the V detects the overflow,
If V=0 no overflow occurred and the n-bit result is correct.
If V=1, an overflow has occurred and the operations needs n+1 bit and only the right most n bits are available. And the (n+1)th bit is the actual sign and shifted out of position.

12. DESIGN PROCEDURE (continue)
BCD Adder
A decimal adder performs the arithmetic summation on decimal numbers in the Binary Coded Decimal (BCD) form.
A decimal adder for BCD receives the two numbers in BCD and calculate the sum in the BCD form. This adder is called BCD Adder
For adding two decimal digits the adder receives 9 bits; 4 bits for each input BCD and 1 bit for carry in, and produces 5 bits where 4 bits for the output BCD and 1 bit for carry out.
Since each BCD digit ranges from 0 to 9, therefore the maximum output is 9+9+1=19, where 1 is for carry in.
To design the decimal adder, the truth table must first be listed and then the relations between inputs and outputs can be deduced .

13. DESIGN PROCEDURE (continue)
BCD Adder (continue)
The summation will be first performed as normal binary operation and after that converted in to BCD form.
The binary sum is listed in the left part of the table and the output bits are labeled 𝑍 1 , 𝑍 2 , 𝑍 4 , and 𝑍 8 . K is the carry out. The subscript is indicating the weights of the bits.

14. DESIGN PROCEDURE (continue)
BCD Adder (continue)
The BCD sum is listed in the right part of the table and the output bits are labeled 𝑆 1 , 𝑆 2 , 𝑆 4 , and 𝑆 8 . C is the carry out. The subscript is indicating the weights of the bits.
From the table the binary sum is identical to the BCD sum where the sum is less then or equal to

15. DESIGN PROCEDURE (continue)
BCD Adder (continue)
For the values grater than the addition of 6(01102) converts to BCD and produces the carry as required.

16. DESIGN PROCEDURE (continue)
BCD Adder (continue)
It is clear from the table the correction is needed if 𝐾=1, 𝑍 8 =1 and 𝑍 2 =1, or 𝑍 8 =1 and 𝑍 4 =1. As shown in the right part of the table all the values that need corrections have a carry out 𝐶=1.
Therefore, 𝑪=𝑲+ 𝒁 𝟖 𝒁 𝟒 + 𝒁 𝟖 𝒁 𝟐 . This carry out signal is used to convert the binary sum to BCD sum by adding 6(01102) to the binary sum.

17. The upper binary adder produces the binary sum.
DESIGN PROCEDURE (continue)
BCD Adder(continue)
The upper binary adder produces the binary sum.
The lower binary adder receives the binary sum and adds if the output carry C=1 to produce BCD sum.
The carry of the lower adder can be ignored since the output carry is already calculated C .
A decimal parallel adder that adds n BCD digits needs n BCD adder stages. C
0110

18. DESIGN PROCEDURE (continue) Binary Multiplier
Multiplication of two binary numbers is performed in a similar way as decimal multiplications.
For two 2-bits numbers A ( 𝐴 1 𝐴 0 ) and B ( 𝐵 1 𝐵 0 ). A has two bits 𝐴 0 and 𝐴 1 and B has two bits 𝐵 0 and 𝐵 1 .
The product is C, which has four bits 𝐶 0 , 𝐶 1 , 𝐶 2 , and 𝐶 3 .
The arithmetic multiplication is performed as follows:
Therefore the logic circuit that can perform this function is:
As shown it is needed 4 AND gates to perform this
function and two HA.

19. DESIGN PROCEDURE (continue) Binary Multiplier (Continue)
Therefore, to build a multiplier that multiplies 4-bits number 𝐵 3 𝐵 2 𝐵 1 𝐵 0 by 3-bits number 𝐴 2 𝐴 1 𝐴 0 , we need 12-AND gates as
shown:
To construct a multiplier that multiplies
J -bits multiplier by K -bits multiplicand we
need 𝐽×𝐾 AND gates and (𝐽−1) k-bits
adders to produce a product (𝐽+𝐾) bits.
Multiplicand
𝐵 𝐵 𝐵 𝐵 0
𝐴 𝐴 𝐴 0
Multiplier
𝐴 0 𝐵 𝐴 0 𝐵 𝐴 0 𝐵 𝐴 0 𝐵 0
𝐴 1 𝐵 𝐴 1 𝐵 𝐴 1 𝐵 𝐴 1 𝐵 0
𝐶 𝑜𝑢𝑡 𝑆 𝑆 𝑆 𝑆 0
𝐴 2 𝐵 𝐴 2 𝐵 𝐴 2 𝐵 𝐴 2 𝐵 0
𝐶 𝑜𝑢𝑡
𝑆 3
𝑆 2
𝑆 1
𝑆 0
𝐶 6
𝐶 5
𝐶 4
𝐶 3
𝐶 2
𝐶 1
𝐶 0

20. DESIGN PROCEDURE (continue) Magnitude Comparator
Magnitude comparator is used to compare between to numbers to decide of they are equal or not and if not which one is greater.
To build a truth table for comparing two n-bits numbers we need to get 2 2𝑛 entries which is a huge quantity of entries.
Therefore, a direct application of the procedure a person uses to compare the relative magnitude of two numbers is adopted here.
For comparing two 4-bits numbers 𝐴= 𝐴 3 𝐴 2 𝐴 1 𝐴 0 and 𝐵= 𝐵 3 𝐵 2 𝐵 1 𝐵 0 , we first check if the corresponding bits in each numbers are equal, which leads to 𝐴 =𝐵. In other words to check if 𝐴 3 = 𝐵 3 , 𝐴 2 = 𝐵 2 , … so on
Therefore to check if 𝑖𝑡ℎ−bit in A is equal to 𝑖𝑡ℎ−bit in B X-NOR function can be used to produce 1 in case of equality 𝑥 𝑖 = 𝐴 𝑖 𝐵 𝑖 + 𝐴 𝑖 ′ 𝐵 𝑖 ′ for 𝑖=0,1,2,3. Hence 𝐴=𝐵 = 𝑥 3 𝑥 2 𝑥 1 𝑥 0 , which gives 1 in case of equality.
Then to check if 𝐴>𝐵 we start by checking the most significant pair of bits 𝐴 3 and 𝐵 3 if they are not equal and 𝐴 3 is 1 then 𝐴 > 𝐵. If this pair of bits are equal then we check the next lower pair 𝐴 2 and 𝐵 2 . The comparison continues until a pair of unequal digits is reached.
Therefore: 𝐴>𝐵 = 𝐴 3 𝐵 3 ′+ 𝑥 3 𝐴 2 𝐵 2 ′+ 𝑥 3 𝑥 2 𝐴 1 𝐵 1 ′+ 𝑥 3 𝑥 2 𝑥 1 𝐴 0 𝐵 0 ′
In the same way: 𝐵>𝐴 = 𝐴 3 ′ 𝐵 3 + 𝑥 3 𝐴 2 ′ 𝐵 2 + 𝑥 3 𝑥 2 𝐴 1 ′ 𝐵 1 + 𝑥 3 𝑥 2 𝑥 1 𝐴 0 ′ 𝐵 0

21. DESIGN PROCEDURE (continue)
Magnitude Comparator (continue)

22. Thanks