1. Lecture 8 Arithmetic Logic Circuits
Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 8

2. Outline Review of Number Systems Adders Combinational Multipliers
Ripple carry
Carry Lookahead
Carry Select
Combinational Multipliers
Arithmetic and Logic Unit (ALU)
General Logic Function Units
READING: Katz 5.2.1, 5.2.2, 5.2.4, 5.3, 5.5, 4.6
ECE C03 Lecture 8

3. Review of Number Systems
Representation of positive numbers same in most systems
Differences in negative numbers
Three major schemes:
sign and magnitude
ones complement
twos complement
Assumptions:
we'll assume a 4 bit machine word
16 different values can be represented
roughly half are positive, half are negative
ECE C03 Lecture 8

4. Sign Magnitude Number System
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/
Representations for 0
Cumbersome addition/subtraction
Must compare magnitudes to determine sign of result
n-1
ECE C03 Lecture 8

5. Twos Complement Representation
like 1's comp
except shifted
one position
clockwise
Only one representation for 0
One more negative number than positive number
ECE C03 Lecture 8

6. Twos Complement Number System
N* = N 4
2 =
7 =
1001 = repr. of -7
sub
Example: Twos complement of 7 4
Example: Twos complement of -7
2 =
-7 =
0111 = repr. of 7
sub
Shortcut method:
Twos complement = bitwise complement + 1
0111 -> > 1001 (representation of -7)
1001 -> > 0111 (representation of 7)
ECE C03 Lecture 8

7. Addition and Subtraction of Numbers
Sign and Magnitude 4
+ 3 7
0100
0011
0111 -4
+ (-3) -7
1100
1011
1111
result sign bit is the
same as the operands'
sign
when signs differ,
operation is subtract,
sign of result depends
on sign of number with
the larger magnitude 4
- 3 1
0100
1011
0001 -4
+ 3 -1
1100
0011
1001
ECE C03 Lecture 8

8. Twos Complement Addition and Subtraction
Twos Complement Calculations 4
+ 3 7
0100
0011
0111 -4
+ (-3) -7
1100
1101
11001
If carry-in to sign =
carry-out then ignore
carry
if carry-in differs from
carry-out then overflow 4
- 3 1
0100
1101
10001 -4
+ 3 -1
1100
0011
1111
Simpler addition scheme makes twos complement the most common
choice for integer number systems within digital systems
ECE C03 Lecture 8

9. Twos Complement Addition and Subtraction
Why can the carry-out be ignored?
-M + N when N > M: n n
M* + N = ( M) + N = (N - M) n
Ignoring carry-out is just like subtracting 2
n-1
-M + -N where N + M < or = 2 n n
-M + (-N) = M* + N* = (2 - M) + (2 - N)
= (M + N) + 2 n n
After ignoring the carry, this is just the right twos compl.
representation for -(M + N)!
ECE C03 Lecture 8

10. Circuits for Binary Addition
Half Adder
With twos complement numbers, addition is sufficient
Half-adder Schematic
ECE C03 Lecture 8

11. Full Adder Cascaded Multi-bit Adder
usually interested in adding more than two bits
this motivates the need for the full adder
ECE C03 Lecture 8

12. Full Adder S = CI xor A xor B
CO = B CI + A CI + A B = CI (A + B) + A B
ECE C03 Lecture 8

13. Full Adder Circuit A + B A + B + CI A S Half Half Adder A B Adder
Standard Approach: 6 Gates A A B B CI CO S CI A B
Alternative Implementation: 5 Gates
A + B
A + B + CI A S S
Half
Half S
Adder
A B
Adder
CI (A + B) B CO CO CI + CO
A B + CI (A xor B) = A B + B CI + A CI
ECE C03 Lecture 8

14. Adder/Subtractor A - B = A + (-B) = A + B + 1 A B B A B B A B B A B B3 B 3 B 3 A 2 B 2 B 2 A 1 B 1 B 1 A B B 1
Sel 1
Sel 1
Sel 1
Sel A B A B A B A B CO + CI CO + CI CO + CI CO + CI
Add/Subtract S S S S S 3 S 2 S 1 S
Overflow
A - B = A + (-B) = A + B + 1
ECE C03 Lecture 8

15. Delay Analysis of Ripple Adder
Carry out of a single stage can be implemented in 2 gate delays
For a 16 bit adder, the 16th bit carry is generated after 16 * 2 = 32 gate delays.
The sum bit takes one additional gate delay to generate the sum of the 16th bit after 15th bit carry
15 * = 31 gate delays
Takes too long - need to investigate FASTER adders!
ECE C03 Lecture 8

16. Carry Lookahead Adder
Critical delay: the propagation of carry from low to high order stages @0 A @1
late
arriving
signal
@N+1 @0 B @N CI CO A
@N+2
two gate delays
to compute CO @0 @0 B @1 C A S @2 B C 1 @2
4 stage
adder A 1 S 1 @3 1 B 1 C 2 @4 A 2 S 2 @5 2 B 2 C 3 @6 A 3 S 3 @7 3
final sum and
carry B 3
ECE C03 Lecture 8 C 4 @8

17. Carry Lookahead Circuit
Critical delay: the propagation of carry from low to high order stages
S0, C1 Valid
S1, C2 Valid
S2, C3 Valid
S3, C4 Valid
worst case
addition T0 T2 T4 T6 T8
T0: Inputs to the adder are valid
T2: Stage 0 carry out (C1)
T4: Stage 1 carry out (C2)
T6: Stage 2 carry out (C3)
T8: Stage 3 carry out (C4)
2 delays to compute sum
but last carry not ready
until 6 delays later
ECE C03 Lecture 8

18. Carry Lookahead Logic
Carry Generate Gi = Ai Bi must generate carry when A = B = 1
Carry Propagate Pi = Ai xor Bi carry in will equal carry out here
Sum and Carry can be reexpressed in terms of generate/propagate:
Si = Ai xor Bi xor Ci = Pi xor Ci
Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + Ci (Ai + Bi)
= Ai Bi + Ci (Ai xor Bi)
= Gi + Ci Pi
ECE C03 Lecture 8

19. Carry Lookahead Logic Reexpress the carry logic as follows:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
Each of the carry equations can be implemented in a two-level logic
network
Variables are the adder inputs and carry in to stage 0!
ECE C03 Lecture 8

20. Carry Lookahead ImplementationAi
1 gate delay Bi
Adder with Propagate and
Generate Outputs
2 gate delays Ci
1 gate delay
Increasingly complex logic C0 P0 G0 C1 P1 G1 C2 P2 G2 C3 P3 P3 P3 P3 C4
ECE C03 Lecture 8 G3

21. Cascaded Carry Lookahead Logic
Carry lookahead
logic generates
individual carries A S @2 B C 1 @3
sums computed
much faster A 1 S 1 @4 B 1 C 2 @3 A 2 S 2 @4 B 2 C 3 @3 A 3 S 3 @4 B 3
ECE C03 Lecture 8 C 4 @3

22. Delay Analysis in Carry Lookahead
Assume a 4-stage adder with CLA
Propagate and generate signals available after 1 gate delays
Carry signals for slices 1 to 4 available after 3 gate delays
Sum signal for slices 1 to 4 after 4 gate delays
ECE C03 Lecture 8

23. Carry Lookahead Logic Cascaded Carry Lookahead4 4 4 4 4 4 4 4 C 16 A
[15-12] B
[15-12] A [1
1-8] B [1
1-8] A
[7-4] B
[7-4] A
[3-0] B
[3-0] C 12 C 8 C 4 C
4-bit
Adder
4-bit
Adder
4-bit
Adder
4-bit
Adder P G P G P G P G @0 4 @8 4 @8 4 @7 4 @4 S
[15-12] S [1
1-8] S
[7-4] S
[3-0] @2 @3 @5 @2 @3 @5 @2 @3 @4 @2 @3 P 3 G 3 C 3 P 2 G 2 C 2 P 1 G 1 C 1 P G C 16 C C 4
Lookahead Carry Unit C @5 @0 P
3-0 G
3-0 @3 @5
4 bit adders with internal carry lookahead
second level carry lookahead unit, extends lookahead to 16 bits
ECE C03 Lecture 8

24. Delay Analysis of Carry Lookahead
Consider a 16-bit adder
Implemented with four stages of 4-bit adders using carry lookahead
Carry in to the highest stage is available after 5 gate delays
Sum from highest stage available at 8 gate delays
COMPARE WITH 32 gate delays for a ripple carry adder
NOTE HOWEVER THIS ASSUMES ALL GATE DELAYS ARE SAME
Not true, delays depand on fan-ins and fan-out
ECE C03 Lecture 8

25. Carry Select Adder
Carry Select adder trades of more hardware for faster carry propagation
Basic idea is to break up 8 bit adder into two 4-bit adder chunks
While the lowest significant 4bit adder computes carry out
In parallel have TWO high-order 4bit adders compute result with two possible cases
carry in of 0
carry in of 1
Depending on final result use a multiplexer to choose correct result
ECE C03 Lecture 8

26. Carry Select Adder
Redundant hardware to make carry calculation go faster C 8
4-Bit
Adder
[7:4]
Adder
Low C 4 C 8 1
4-Bit
Adder
[7:4]
Adder
High 1 1 1 1 4
2:1 Mux C 4
4-Bit
Adder
[3:0] C C 8 S 7 S 6 S 5 S 4 S 3 S 2 S 1 S
compute the high order sums in parallel
one addition assumes carry in = 0
the other assumes carry in = 1
ECE C03 Lecture 8

27. Delay Analysis in Carry Select Adders
Consider an 8 bit adder using two 4 bit chunks
Assume each internal 4-bit adder uses carry lookahead
needs 4 gate delays to compute sums and 3 gate delays to compute the stage carry-out
The 2:1 multiplexers add 2 more gate delays
Hence 8-bit sum is valid after 6 gate delays
COMPARED with 7 gate delays in a carry lookahead unit and 16 gate delays of a ripple carry adder
AGAIN ASSUME that all gate delays are equal, not true in practice
ECE C03 Lecture 8

28. Theory of Multiplication
Basic Concept
multiplicand
multiplier
(13)
(11)
1101
product of 2 4-bit numbers
is an 8-bit number *
1101
Partial products
0000
1101
(143)
ECE C03 Lecture 8

29. Combinational Multiplier
Partial Product Accumulation
A3 B3 A1 B1
A1 B0
A0 B1 A0 B0
A0 B0
A3 B2
A2 B3
A3 B1
A2 B2
A1 B3 A3 B3
A2 B0
A2 B1
A1 B2
A0 B3 A2 B2
A2 B0
A1 B1
A0 B2 S7 S6 S5 S4 S3 S2 S1 S0
ECE C03 Lecture 8

30. Partial Product Accumulation
Note use of parallel carry-outs to form higher order sums
12 Adders, if full adders, this is 6 gates each = 72 gates
16 gates form the partial products
total = 88 gates!
ECE C03 Lecture 8

31. Combinational Multiplier
Another Representation of the Circuit
Building block: full adder + and
4 x 4 array of building blocks
ECE C03 Lecture 8

32. Arithmetic Logic Unit Design
Sample ALU
Logical and Arithmetic Operations
Not all operations appear useful, but "fall out" of internal logic
ECE C03 Lecture 8

33. Arithmetic Logic Unit Design
Sample ALU M 1 S1 S0 Ci X Ai Bi Fi
Ci+1
Traditional Design Approach X 1 X 1 X
Truth Table & Espresso X X 1 X 1 X
.i 6
.o 2
.ilb m s1 s0 ci ai bi
.ob fi co
.p 23 .e X 1 X
23 product terms! X X 1 X X
Equivalent to
25 gates 1 X 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ECE C03 Lecture 8 1 1 1

34. Arithmetic Logic Unit Design
Sample ALU
Multilevel Implementation
.model alu.espresso
.inputs m s1 s0 ci ai bi
.outputs fi co
.names m ci co [30] [33] [35] fi
.names m ci [30] [33] co
-1-1 1
--11 1
111- 1
.names s0 ai [30]
01 1
10 1
.names m s1 bi [33]
111 1
.names s1 bi [35]
0- 1
-0 1
.end
\S1
[35] M Ci
\Bi Ci
[33]
\Co Ci M
[30] Co
[30] S1
[33]
[33]
[33] Bi Fi M
\Co Ci
[30]
[30]
[35] S0
[30]
\Co Ai
\[30]
\[35]
12 Gates
ECE C03 Lecture 8

35. Arithmetic Logic Unit Design
Sample ALU
Clever Multi-level Logic Implementation
S1 = 0 blocks Bi
Happens when operations involve Ai
only
Same is true for Ci when M = 0
Addition happens when M = 1
Bi, Ci to Xor gates X2, X3
S0 = 0, X1 passes A
S0 = 1, X1 passes A S1 Bi S0 Ai M Ci A1 X1 A2 X2 A3 A4
Arithmetic Mode:
Or gate inputs are Ai Ci and
Bi (Ai xor Ci) X3 O1
Logic Mode:
Ci+1 Fi
Cascaded XORs form output from
Ai and Bi
ECE C03 Lecture 8
8 Gates (but 3 are XOR)

36. Arithmetic Logic Unit Design
74181 TTL ALU
ECE C03 Lecture 8

37. Arithmetic Logic Unit Design
74181 TTL ALU
Note that the sense of the carry in and out are
OPPOSITE from the input bits 19 A3
182 21 13 A2
181 F3 6 P3 23 11 A1 F2 15 2 10 P2 A0 F1 7 P 18 9 2 B3 F0 P1 10 20 4 G B2
A=B 14 P0 22 B1
Cn+4 16 5 G3 1 B0
Cn+z 9 14 G 17 G2 7 Cn
Cn+y 11 1 P 15 G1 8 M
Cn+x 12 3 G0 S3 S2 S1 S0 13 Cn 3 4 5 6
Fortunately, carry lookahead generator
maintains the correct sense of the signals
ECE C03 Lecture 8

38. Arithmetic Logic Unit Design
182 P3 P2 P1 P0 G3 G2 G1 G0 Cn
Cn+z
Cn+x P G
Cn+y 13 3 1 14 5 4 2 15 6 12 11 9 10 7
181 A3 A2 A1 A0 B3 B2 B1 B0 M S3 S2 S1 S0 F3 F2 F1 F0
A=B
Cn+4 8 16 17 18 19 20 21 22 23
16-bit ALU with Carry Lookahead
C16
Cn+4 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23
181 A3 A2 A1 A0 B3 B2 B1 B0 Cn M S3 S2 S1 S0 F3 F2 F1 F0
A=B G P 19 21 F3 13 23 F2 11 2 F1 10 18 F0 9 20 22
A=B 14 1
Cn+4 16 C0 7 G 17 8 P 15 S0 3 4 5 6
ECE C03 Lecture 8

39. General Logical Function Unit
Statement of the Problem:
3 control inputs: C0, C1, C2
2 data inputs: A, B
1 output: F
Similar to the main computation unit in a Microprocessor
ECE C03 Lecture 8

40. Logical Function Unit 8:1 Mux Formulate as a truth table
Choose implementation technology
4 TTL packages:
4 x 2-input NAND
4 x 2-input NOR
2 x 2-input XOR
8:1 MUX A B A B A B + 5 V D D 1 D 2 D 3 D 4 D 5 D 6 D 7 S C 2
8:1 Mux S 1 C 1 E N Q O S 2 C F
ECE C03 Lecture 8

41. Logical Function Unit Follow implementation procedure1 2
A B 00 01 11 10 C =0 00 1 1
F = C2' A' B' + C0' A B'
+ C0' A' B + C1' A B 01 1 1 1 1 11 1 1
5 gates, 5 inverters
Also four packages:
4 x 3-input NAND
1 x 4-input NAND
Alternative: PAL/PLA
single package 10 1 1 1 1 C 1 2
A B 00 01 11 10 C =1 00 1 1 01 11 1 1 10
ECE C03 Lecture 8

42. Summary Review of Arithmetic Number Representation
Adders - Ripple carry, Carry Lookahead, Carry Select Adders
Combinational multipliers
Arithmetic and Logic Unit (ALU)
General function circuits
NEXT LECTURE: Memory Elements and Clocking
READING: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2
ECE C03 Lecture 8