1. Digital Kommunikationselektronik TNE027 Lecture 2 1 FA x n –1 c n c n1- y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position Ripple-Carry Adder (See Fig. 2.6) Longest delay (Critical-path delay): d c(n) = n×d carry = 2n gate delays d s(n-1) = (n-1)× d carry +d sum = 2n gate delays Binary Adders

2. Digital Kommunikationselektronik TNE027 Lecture 2 2 Full adder

3. Digital Kommunikationselektronik TNE027 Lecture 2 3 Fast-carry logic in FPGAs –The fast-carry logic is about a magnitude faster than the delay through a regular logic LUT. See Fig. 2.7. FCL c n c n1- c n c 2 c 2 c 1 x n –1 y n1– x 1 y 1 x 0 y 0 c 1 c 0 x 1 y n1– x 1 y 1 x 0 y 0 XOR s n-1 XOR s 0 s 1

4. Digital Kommunikationselektronik TNE027 Lecture 2 4 Instruction pipeline for a RISC Instruction fetch Instruction decode and register fetch Execution and address calculation Memory access ResultW rite back IFIDEXMEMWB Instruction Pipelining Total latency: Total delay time from instruction fetch to result write back to a register Throughput (maximum frequency, registered performance): Number of results (instructions) per second

5. Digital Kommunikationselektronik TNE027 Lecture 2 5 Instruction Pipelining (continued)

6. Digital Kommunikationselektronik TNE027 Lecture 2 6 Pipelined adders –Pipelining principle can be applied to FPGA designs at little or no additional cost since each logic element contains a flip-flop, which is otherwise unused. –An arithmetic operation is broken into small primitive operations. The result of each primitive operations is saved in registers after each pipeline stage. –If one part of the data is not processed at a pipeline stage, this part of data should still be saved after the pipeline stage. See Fig. 2.9. Arithmetic Pipelining

7. Digital Kommunikationselektronik TNE027 Lecture 2 7 Modulo Adders –Building block of RNS-DSP design –Modulo operation is performed by (a) an extra adder or (b) a ROM look-up table. See Fig.2.11.

8. Digital Kommunikationselektronik TNE027 Lecture 2 8 Multiplication by 2 k can be implemented by shifting the bits of the operand to the left by k. Division by 2 k can be implemented by shifting the bits of the operand to the right by k. For signed numbers, it is necessary to preserve the sign. This is done by shifting the bits to the right and filling from the left with the value of the sign bit. Multiplication and Division by 2 k

9. Digital Kommunikationselektronik TNE027 Lecture 2 9 Binary Multipliers Multiplication of unsigned numbers  1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 1 0 Multiplicand M Multiplier Q Product P (14) (11) (154) Multiplication of unsigned numbers by hand

10. Digital Kommunikationselektronik TNE027 Lecture 2 10  1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 Multiplicand M Multiplier Q Product P (11) (14) (154) + 1 0 1 0 1 0 0 + 0 1 0 1 0 1 1 1 0 + Partial product 0 Partial product 1 Partial product 2 Multiplication of unsigned numbers Multiplication for implementation in hardware

11. Digital Kommunikationselektronik TNE027 Lecture 2 11 Shift-add multiplier –Serial/parallel multiplier N full adders + shift registers –Serial/serial multiplier One carry-save adder + shift registers –Parallel/parallel multiplier (array multiplier) N 2 full adders (See Fig. 2.13.) Fast array multiplier for FPGAs (See Fig. 2.14.) Multiplier blocks P = Y  X = (Y 2 2 N +Y 1 ) (X 2 2 N +X 1 ) = Y 2 X 2 2 2N + (Y 2 X 1 +Y 1 X 2 ) 2 N + Y 1 X 1

12. Digital Kommunikationselektronik TNE027 Lecture 2 12 Carry-save adder Serial/serial multiplier Multiplicant & Multiplier Carry-save adder Partial product Full adder a b D Q Q Carry-out Clock Reset D Q Q s Y 2 Y 1 Sum bit y 2 y 1

13. Digital Kommunikationselektronik TNE027 Lecture 2 13 Serial/parallel multiplier using carry-save adders FA D D & D D & D... A n-2 A0A0 FA D & A n-1 B n-1 B n-2...B 0 shift... Multiplicant A n-1 A n-2...A 0 Multiplier B n-1 B n-2...B 0

14. Digital Kommunikationselektronik TNE027 Lecture 2 14 Binary Dividers Division –Division is the most complex operation among the 4 basic arithmetic operations. –Let N denote numerator and D denominator, two results are produced: the quotient Q and the remainder R: N / D = Q + R / D

15. Digital Kommunikationselektronik TNE027 Lecture 2 15 –In division, each quotient bit is determined in a sequential “trial-and-error” procedure. (In multiplication, all partial products can be produced parallel.) –Result should be constrained: Q  N and |R|  D –For signed numbers, R and N are assumed to have the same sign.

16. Digital Kommunikationselektronik TNE027 Lecture 2 16 Division Algorithms Linear Convergence Division Algorithms Restoring divider –a trial-and-error method translated directly from the “pencil-and-paper” method See example 2.18. –The main disadvantage of the restoring divider is that we need two steps, subtract and add (i.e., restore), to determine one quotient bit.

17. Digital Kommunikationselektronik TNE027 Lecture 2 17 Nonperforming divider –A temporary remainder value is tested before the remainder register is updated. –Note that the following VHDL code describes a combinational circuit. t := r – d;--temporary remainder value IF t >= 0 THEN -- Nonperforming test r := t;-- Update remainder q := q * 2 + 1;-- Shift left and add 1 ELSE q :=q * 2;-- Shift left END IF;

18. Digital Kommunikationselektronik TNE027 Lecture 2 18 Nonrestoring divider –Always perform the subtraction. –If the remainder is negative, perform an addition of d k /2 in the next step, instead of the restoring addition of d k in the present step and the subtraction of d k /2 in the next step. –The quotient bit can be positive or negative, i.e., d k =  1, but not zero. This is a signed-digit representation. The negative ones can be saved in the quotient register as zeros.

19. Digital Kommunikationselektronik TNE027 Lecture 2 19 –The signed-digit representation should be converted to 2’s complement representation. For example: q SD =1111 is saved as 1001 in the quotient register. To convert: 1001 (positive ones) – 0110 (negative ones) 0011 alternatively: 2 * 1001 + 1 1001 + 1 10011 –Correct remainder if r < 0: r := r + D and q := q – 1.

20. Digital Kommunikationselektronik TNE027 Lecture 2 20 Fast Divider Design Division through multiplication with reciprocal of denominator –The reciprocal can be computed via a look-up table for small bit width. –One can use Newton Algorithm to compute the reciprocal. f(x) = 1/x – D  0 x ∞ = 1/D x k+1 = x k – f(x k ) / f ´(x k ) x k+1 = x k (2 – D  x k )

21. Digital Kommunikationselektronik TNE027 Lecture 2 21 Division by Convergence –Both numerator N and denominator D are multiplied by approximation factors f k. –After a sufficient number of iterations k (quadratic convergence), D Π f k  1 and N Π f k  Q Algorithm: 1)Normalize N and D such that D is close to 1. 2)Initialize x 0 = N and t 0 = D. 3)Repeat the following loop until x k shows the desired precision. f k = 2 – t k x k+1 = x k  f k t k+1 = t k  f k See Example 2.21.