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UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS.

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Presentation on theme: "UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS."— Presentation transcript:

1 UNIT 2

2 ADDITION & SUBTRACTION OF SIGNED NUMBERS

3 xixi YiYi carry c i sum s i carry-out c i+1 00000 00110 01010 01101 10010 10101 11001 11111

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5 Logic for single stage

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7 n-bit ripple carry adder A cascaded connection of n full adder blocks can be used to add n-bit numbers.since carry propagate or ripple through the adder it is called an n-bit ripple carry adder.

8 n-bit ripple carry adder

9 DESIGN OF FAST ADDERS

10 Two approaches to reduce delay in adders – 1 st approach-Fastest possible electronic technology in implementing ripple carry logic design – 2 nd approach-Use an augmented logic gate network structure that is larger

11 MULTIPLICATION OF POSITIVE NUMBERS

12 Product of n digit numbers can be accommodated in 2n digits Product of 4bit numbers will fit into 8bits Refer pg-378 4 th para alone for register configuration diagram

13 Manual multiplication 1 1 0 1 x multiplicand M 1 0 1 1 multiplier Q 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 1 Product P

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16 REGISTER CONFIGURATION

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18 SIGNED OPERAND MULTIPLICATION BOOTH ALGORITHM

19 BOOTH MULTIPLIER TABLE

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22 FAST MULTIPLICATION 1.BIT PAIR RECODING OF MULTIPLIER 2.CARRY SAVE ADDITION OF SUMMANDS

23 1.BIT PAIR RECODING OF MULTIPLIER 2.CARRY SAVE ADDITION OF SUMMANDS Have been used in various ways by the high performance processor to reduce the time needed to perform multiplication

24 BIT PAIR RECODING OF MULTIPLIER

25 A technique called Bit pair recoding halves the maximum number of summands It is derived directly from booth algorithm

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30 CARRY SAVE ADDITION OF SUMMANDS

31 Multiplication requires the addition of several summands A technique called carry save addition(CSA) speeds up the addition process Instead of letting the carries ripples along the rows, they can be saved and introduced into the next row,at the correct weighted position

32 Delay through carry save array is somewhat less than delay through ripple carry array A more significant reduction in delay can be achieved as follows – Consider addition of many summands,as required in multiplication of longer operand – Group the summands in three and perform carry save addition on each of these group

33 In parallel to generate a set of S and C – Next we group all of the S and C vectors into three and perform carry save addition on them,generate further set of S and C - We continue this process until there are only two vectors remaining

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38 INTEGER DIVISION 1.Restoring Division 2.Non Restoring Division 1.

39 Restoring Division

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43 Non Restoring Division

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