CSE477 L01 Introduction.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 01: Introduction Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L01 Introduction.2Irwin&Vijay, PSU, 2003 Course Contents  Introduction to digital integrated circuits l CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory circuit design.  Course goals l Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability  Course prerequisites l EE 310. Electronic Circuit Design l CSE 471. Logic Design of Digital Systems

CSE477 L01 Introduction.3Irwin&Vijay, PSU, 2003 Course Administration  Instructor:Mary Jane Irwin Pond Lab Office Hrs: T 16:00-17:00 & W 9:30-10:45  TA:Feihui Li 128 Hammond Office Hrs: TBD  Labs: Accounts on 101 Pond Lab machines  URL:  Text: Digital Integrated Circuits, 2 nd Edition Rabaey et. al., ©2003  Slides:pdf on the course web page after lecture

CSE477 L01 Introduction.4Irwin&Vijay, PSU, 2003 Grading Information  Grade determinates l Midterm Exam~25% -Monday, October 20 th, 20:15 to 22:15, Location TBD l Final Exam~25% -Monday, December 15 th, 10:10 to noon, Location TBD l Homeworks/Lab Assignments (5)~20% -Due at the beginning of class (or, if submitted electronically, by 17:00 on the due date). No late assignments will be accepted. l Design Project (teams of ~2)~25% l In-class pop quizzes~ 5%  Please let me know about exam conflicts ASAP  Grades will be posted on the course homepage l Must submit request for change of grade after discussions with the TA (Homeworks/Lab Assignments) or instructor (Exams) l December 9 th deadline for filing grade corrections; no requests for grade changes will be accepted after this date

CSE477 L01 Introduction.5Irwin&Vijay, PSU, 2003 Background from CSE471 and EE310  Basic circuit theory l resistance, capacitance, inductance l MOS gate characteristics  Hardware description language l VHDL or verilog  Use of modern EDA tools l simulation, synthesis, validation (e.g., Synopsys) l schematic capture tools (e.g., LogicWorks)  Logic design l logical minimization, FSMs, component design

CSE477 L01 Introduction.6Irwin&Vijay, PSU, 2003 Course Structure  Design and tool intensive class l Micromagic (MMI) “max” and “sue” for layout -Online documentation and tutorials l HSPICE for circuit simulation l unix (Sun/Solaris) operating system environment  Lectures: l 2 weeks on the CMOS inverter l 3 weeks on static and dynamic CMOS gates l 2 weeks on C, R, and L effects l 2 week on sequential CMOS circuits l 2 weeks on design of datapath structures l 2 weeks on memory design l 1 week on design for test, margining, scaling, trends l 1 week exams

CSE477 L01 Introduction.7Irwin&Vijay, PSU, 2003 “Executives might make the final decisions about what would be produced, but engineers would provide most of the ideas for new products. After all, engineers were the people who really knew the state of the art and who were therefore best equipped to prophesy changes in it.” The Soul of a New Machine, Kidder, pg 35

CSE477 L01 Introduction.8Irwin&Vijay, PSU, 2003 Transistor Revolution  Transistor –Bardeen (Bell Labs) in 1947  Bipolar transistor – Schockley in 1949  First bipolar digital logic gate – Harris in 1956  First monolithic IC – Jack Kilby in 1959  First commercial IC logic gates – Fairchild 1960  TTL – 1962 into the 1990’s  ECL – 1974 into the 1980’s

CSE477 L01 Introduction.9Irwin&Vijay, PSU, 2003 MOSFET Technology  MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935  CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations)  PMOS in 1960’s (calculators)  NMOS in 1970’s (4004, 8080) – for speed  CMOS in 1980’s – preferred MOSFET technology because of power benefits  BiCMOS, Gallium-Arsenide, Silicon-Germanium  SOI, Copper-Low K, strained silicon, …

CSE477 L01 Introduction.10Irwin&Vijay, PSU, 2003 Moore’s Law  In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 months (i.e., grow exponentially with time).  Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) l 16 Million transistors (Ultra Sparc III) l 42 Million, 2 GHz clock (Intel P4) l 140 Million transistor (HP PA-8500)

CSE477 L01 Introduction.11Irwin&Vijay, PSU, 2003 Moore’s Law in Microprocessors Pentium® proc P Year Transistors (MT) 2X growth in 1.96 years! # transistors on lead microprocessors double every 2 years Courtesy, Intel

CSE477 L01 Introduction.12Irwin&Vijay, PSU, 2003 Intel 4004 Microprocessor (10000 nm)

CSE477 L01 Introduction.13Irwin&Vijay, PSU, 2003 Intel P2 Microprocessor (280 nm)

CSE477 L01 Introduction.14Irwin&Vijay, PSU, 2003 State-of-the Art: Lead Microprocessors

CSE477 L01 Introduction.15Irwin&Vijay, PSU, 2003 Evolution in DRAM Chip Capacity  m  m  m  m  m  m 0.13  m 0.1  m 0.07  m human memory human DNA encyclopedia 2 hrs CD audio 30 sec HDTV book page 4X growth every 3 years!

CSE477 L01 Introduction.16Irwin&Vijay, PSU, 2003 Die Size Growth Pentium ® proc P Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

CSE477 L01 Introduction.17Irwin&Vijay, PSU, 2003 Clock Frequency Lead microprocessors frequency doubles every 2 years P6 Pentium ® proc Year Frequency (Mhz) 2X every 2 years Courtesy, Intel

CSE477 L01 Introduction.18Irwin&Vijay, PSU, 2003 Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel Power delivery and dissipation will be prohibitive

CSE477 L01 Introduction.19Irwin&Vijay, PSU, 2003 Power Density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

CSE477 L01 Introduction.20Irwin&Vijay, PSU, 2003 Technology Directions: “Old” SIA Roadmap Year Feature size (nm) Mtrans/cm Chip size (mm 2 ) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years)

CSE477 L01 Introduction.21Irwin&Vijay, PSU, 2003 Why Scaling?  Technology shrinks by ~0.7 per generation  With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly  Cost of a function decreases by 2x  But … l How to design chips with more and more functions? l Design engineering population does not double every two years…  Hence, a need for more efficient design methods l Exploit different levels of abstraction

CSE477 L01 Introduction.22Irwin&Vijay, PSU, 2003 Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

CSE477 L01 Introduction.23Irwin&Vijay, PSU, 2003 Design Productivity Trends Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Complexity Courtesy, ITRS Roadmap Complexity outpaces design productivity

CSE477 L01 Introduction.24Irwin&Vijay, PSU, 2003 Major Design Challenges  Microscopic issues l ultra-high speeds l power dissipation and supply rail drop l growing importance of interconnect l noise, crosstalk l reliability, manufacturability l clock distribution  Macroscopic issues l time-to-market l design complexity (millions of gates) l high levels of abstractions l reuse and IP, portability l systems on a chip (SoC) l tool interoperability YearTech. (nm) ComplexityFrequency3 Yr. Design Staff Size Staff Costs M Tr.400 MHz210$90 M M Tr.500 MHz270$120 M M Tr.600 MHz360$160 M M Tr.800 MHz800$360 M

CSE477 L01 Introduction.25Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Design metrics -Reading assignment – 1.3  Reminders l Hands on max tutorial -?Tuesday? evening from 7:00? to 9:00? pm in 101 Pond Lab l HW1 due September 16 th l Project team and title due September 18 th l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Please let me know ASAP (via ) if you have a conflict