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EE5780 Advanced VLSI Computer-Aided Design
Dr. Shiyan Hu Office: EERC 518 Introduction Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.
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Class Time and Office Hour
EE141 Class Time and Office Hour Class Time: MWF 14:05-14:55 (EERC 216) Office Hours: MWF 15:00-15:50 or by appointment, office: EERC 518 Textbook (suggested) Handbook of Algorithms for Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2008 Grading: Homework 25% Project % Exams %
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EE141 Course Website Contact information of instructor EERC 518 Instructor’s webpage:
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EE141 Introduction Why is designing digital ICs different today than it was before? What is the challenge?
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The Transistor Revolution
First transistor Bell Labs, 1948
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The First Integrated Circuit
First IC Jack Kilby Texas Instruments 1958
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EE141 Intel 4004 Microprocessor 1971 1000 transistors 1 MHz operation
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Intel 8080 Microprocessor 1974 4500 transistors
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Intel Pentium Microprocessor
2000 42 million transistors 1.5 GHz
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Modern Chip
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Basic Components In VLSI Circuits
Devices Transistors Logic gates and cells Function blocks Interconnects Local interconnects Global interconnects Clock interconnects Power/ground nets
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CMOS transistors 3 terminals in CMOS transistors: G: Gate D: Drain
S: Source nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)
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An Example: CMOS Inverter
F = X’ +Vdd GRD F = X’ X Logic symbol Operation: X=1 nMOS switch conducts (pMOS is open) and draws from GRD F=0 X=0 pMOS switch conducts (nMOST is open) and draws from +Vdd F=1 Transistor-level schematic
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Cross-Section of A Chip
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EE141 Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months Not true any more Interconnect delay dominates Variations
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Moore’s law in Microprocessors
EE141 Moore’s law in Microprocessors 1000 2X growth in 1.96 years! 100 10 P6 Pentium® proc Transistors (MT) 1 486 386 0.1 286 Transistors on Lead Microprocessors double every 2 years 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel
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ITRS Prediction 17
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Lead Microprocessors frequency doubles every 2 years
Not true any more! 10000 Doubles every 2 years 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 10 386 8085 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel
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Interconnects Dominate
300 250 200 Interconnect delay 150 Delay (psec) 100 Transistor/Gate delay 50 19 [CF] The problem is that at 0.18u and below interconnect overwhelmingly dominates the delay on a chip, and current design methods have been created to only consider the delay from the transistor gate. So, you never get a true timing picture of the performance of your chip during your design iterations. The impact of this is difficulty in achieving Design Closure. This is important because it will cause delay in the delivery of your chip and uncertainty in its performance. [Michel] The above graphic shows how interconnect delay accounts for most of the delay in chips today and will continue to do so with advancing technologies. This is mainly due to the shrinking gate sizes which reduces the gate capacitance and the shrinking widths and spacing of the interconnect which increases the overall interconnect capacitance. Please turn to the next slide titled “and Coupling Dominates Interconnect”. 0.8 0.5 0.35 0.25 0.25 0.18 0.15 Technology generation (m) Source: Gordon Moore, Chairman Emeritus, Intel Corp. 19 19
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Lead Microprocessors power continues to increase
EE141 Power Dissipation 100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel
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Power is a major problem
EE141 Power is a major problem 100000 18KW 5KW 10000 1.5KW 1000 500W Pentium® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel
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Power density Rocket Nozzle Nuclear Reactor Hot Plate 10000 1000
Power Density (W/cm2) 100 8086 10 Hot Plate 4004 P6 8008 8085 386 Pentium® proc 286 486 8080 1 1970 1980 1990 2000 2010 Year Courtesy, Intel
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Chip Thermal
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Logic Design and Synthesis
VLSI Design Cycle System Specification e.g., Verilog X=(AB*CD)+(A+D)+(A(B+C)) Y=(A(B+C))+AC+D+A(BC+D)) Functional Design Logic Design and Synthesis
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VLSI Design Cycle (cont.)
Physical Design Fabrication Packaging
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Physical Design Given a circuit after logic synthesis, to convert it into a layout (i.e., determine the physical location of each gate and the interconnects between gates). PD
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Nanoscale Challenges Interconnect-limited designs Power barrier
Interconnect performance limitation Interconnect modeling complexity Interconnect reliability (signal integrity) Power barrier High degree of on-chip integration Complexity and productivity System on a chip Variations
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Robust Design For Variations
The difference between the designed value and the actual value Robust design Mitigate or compensate for variations Robustness for lithography-induced variations
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Chip Design and Fabrication
Fabricated Chip Lithography Process Designed Chip Layout 29
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Photo-Lithography Process
optical mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step 30
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Lithography System 193nm wavelength Illumination 45nm features Mask
Objective Lens Aperture Wafer 31
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What you design is NOT what you get!
Mask v.s. Printing 0.25µ 0.18µ 0.13µ 90-nm 65-nm Layout What you design is NOT what you get! 32
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Tolerable variation (nm)
Motivation Chip design cannot be fabricated Gap Lithography technology: 193nm wavelength VLSI technology: 45nm features Lithography induced variations Impact on timing and power Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported. Technology node 130nm 90nm 65nm 45nm Gate length (nm) Tolerable variation (nm) 90 5.3 53 3.75 35 2.5 28 2 Wavelength (nm) 248 193 33 33
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Gap: Lithography Tech. v.s. VLSI Tech.
28nm, tolerable distortion: 2nm 193nm Increasing gap Printability problem (and thus variations) more severe! 34
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Summary CAD is necessary to design a chip with billion transistors.
EE141 Summary CAD is necessary to design a chip with billion transistors. Digital integrated circuit design challenges in nanoscale regime Timing Power Reliability Short design turn-around time
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