2. EE414 VLSI Design Introduction Introduction to VLSI Design [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

3. EE414 VLSI Design What is this course is about? l Introduction to digital integrated circuits. »CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. l What will you learn? »Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

4. EE414 VLSI Design Digital Integrated Circuits l Introduction: Issues in digital design l The CMOS inverter l Combinational logic structures l Sequential logic gates l Design methodologies l Interconnect: R, L and C l Timing l Arithmetic building blocks l Memories and array structures

5. EE414 VLSI Design l What is meant by VLSI? l Brief history of evolution l Today’s Chips l Moore’s Law l Machines Making Machines l VLSI Facts of Life Digital Integrated Circuits

6. EE414 VLSI Design What is a VLSI Circuit? VERY LARGE SCALE A circuit that has 10k ~ 10M transistors on a single chip Still growing as number of transistors on chip quadruple every 24 months (Moore’s law!) Technique where many circuit components and the wiring that connects them are manufactured simultaneously on a compact chip (die) INTEGRATED CIRCUIT

7. EE414 VLSI Design Brief History The First Computer: Babbage Difference Engine (1832) Executed basic operations (add, sub, mult, div) in arbitrary sequences Operated in two-cycle sequence, “Store”, and “Mill” (execute) Included features like pipelining to make it faster. Complexity: 25,000 parts. Cost: £17,470 (in 1834!)

8. EE414 VLSI Design The Electrical Solution More cost effective Early systems used relays to make simple logic devices Still used today in some train safety systems The Vacuum Tube Originally used for analog processing Later, complete digital computers realized High Point of Tubes: The ENIAC 18,000 vacuum tubes 80 ft long, 8.5 ft high, several feet wide

9. EE414 VLSI Design ENIAC - The first electronic computer (1946)

10. EE414 VLSI Design Dawn of the Transistor Age 1951: Shockley develops junction transistor which can be manufactured in quantity. 1954: TI makes first silicon transistor (price $2.50) 1945: Shockley’s lab established 1947: Bardeen and Brattain create point-contact transistor w/two PN junctions. Gain = 18

11. EE414 VLSI Design Early Integration Jack Kilby, working at Texas Instruments, invented a monolithic “integrated circuit” in July 1959. He had constructed the flip-flop shown in the patent drawing above.

12. EE414 VLSI Design Early Integration In mid 1959, Noyce develops the first true IC using planar transistors, back-to-back pn junctions for isolation, diode-isolated silicon resistors and SiO2 insulation with evaporated metal wiring on top

13. EE414 VLSI Design Practice Makes Perfect 1961: TI and Fairchild introduce first logic IC’s (cost ~ $50 in quantity!). This is a dual flip-flop with 4 transistors. 1963: Densities and yields improve. This circuit has four flip-flops.

14. EE414 VLSI Design Practice Makes Perfect 1967: Fairchild markets the first semi-custom chip. Transistors (organized in columns) can be easily rewired to create different circuits. Circuit has ~150 logic gates. 1968: Noyce and Moore leave Fairchild to form Intel. They raise $3M in two days and move to Santa Clara. By 1971 Intel had 500 employees; by 1983, 21,500 employees and $1.1B in sales.

15. EE414 VLSI Design The Big Bang 1970: Intel starts selling a 1k bit RAM, the 1103. Its density and cost make it the only game in town. 1971: Ted Hoff at Intel designed the first microprocessor. The 4004 had 4-bit busses and a clock rate of 108 KHz. It had 2300 transistors and was built in a 10 u process.

16. EE414 VLSI Design Exponential Growth 1972: 8088 introduced. Had 3,500 transistors supporting a byte- wide data path. 1974: Introduction of the 8080. Had 6,000 transistors in a 6 u process. The clock rate was 2 MHz.

17. EE414 VLSI Design Today Many disciplines have contributed to the current state of the art in VLSI Design: Solid State Physics Materials Science Lithography and fab Device modeling Circuit design and layout Architecture design Algorithms CAD tools To come up with chips like:

18. EE414 VLSI Design Today Intel Pentium ~3.5M transistors

19. EE414 VLSI Design Today Intel Pentium Pro Actually a MCM comprising of microprocessor and L2 cache Why not make it on one chip?

20. EE414 VLSI Design Today Sun UltraSparc

21. EE414 VLSI Design Today Intel Pentium II Intel Pentium IV

22. EE414 VLSI Design Evolution of Electronics

23. EE414 VLSI Design Moore’s Law lIIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lHHe made a prediction that semiconductor technology will double its effectiveness every 18 months

24. EE414 VLSI Design Moore’s Law Electronics, April 19, 1965.

25. EE414 VLSI Design Evolution in Complexity

26. EE414 VLSI Design Transistor Counts 1,000,000 100,000 10,000 1,000 10 100 1 19751980198519901995200020052010 8086 80286 i386 i486 Pentium ® Pentium ® Pro K 1 Billion Transistors Source: Intel Projected Pentium ® II Pentium ® III Courtesy, Intel

27. EE414 VLSI Design Moore’s law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel

28. EE414 VLSI Design Die Size Growth 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 19701980199020002010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

29. EE414 VLSI Design Frequency Lead Microprocessors frequency doubles every 2 years Courtesy, Intel

30. EE414 VLSI Design Power Dissipation Lead Microprocessors power continues to increase Courtesy, Intel

31. EE414 VLSI Design Power will be a major problem Power delivery and dissipation will be prohibitive Courtesy, Intel

32. EE414 VLSI Design Power density Power density too high to keep junctions at low temp Courtesy, Intel

33. EE414 VLSI Design Not Only Microprocessors Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Cell Phone

34. EE414 VLSI Design Challenges in Digital Design “Microscopic Problems” Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different “Macroscopic Issues” Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. …and There’s a Lot of Them!  DSM  1/DSM ?

35. EE414 VLSI Design Productivity Trends Complexity outpaces design productivity Courtesy, ITRS Roadmap

36. EE414 VLSI Design Why Scaling? l Technology shrinks by 0.7/generation l With every generation can integrate 2x more functions per chip; chip cost does not increase significantly l Cost of a function decreases by 2x l But … »How to design chips with more and more functions? »Design engineering population does not double every two years… l Hence, a need for more efficient design methods »Exploit different levels of abstraction

37. EE414 VLSI Design Design Abstraction Levels

38. EE414 VLSI Design Design Metrics l How to evaluate performance of a digital circuit (gate, block, …)? »Cost »Reliability »Scalability »Speed (delay, operating frequency) »Power dissipation »Energy to perform a function

39. EE414 VLSI Design Cost of Integrated Circuits l NRE (non-recurrent engineering) costs »design time and effort, mask generation »one-time cost factor l Recurrent costs »silicon processing, packaging, test »proportional to volume »proportional to chip area

40. EE414 VLSI Design NRE Cost is Increasing

41. EE414 VLSI Design Die Cost Single die Wafer From http://www.amd.com Going up to 12” (30cm)

42. EE414 VLSI Design Cost per Transistor 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 1982198519881991 1994 199720002003200620092012 cost: ¢-per-transistor Fabrication capital cost per transistor (Moore’s law)

43. EE414 VLSI Design Yield

44. EE414 VLSI Design Defects  is approximately 3

45. EE414 VLSI Design Some Examples (1994) ChipMetal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer YieldDie cost 386DX 20.90$9001.04336071%$4 486 DX2 30.80$12001.08118154%$12 Power PC 601 40.80$17001.312111528%$53 HP PA 7100 30.80$13001.01966627%$73 DEC Alpha 30.70$15001.22345319%$149 Super Sparc 30.70$17001.62564813%$272 Pentium 30.80$15001.5296409%$417

46. EE414 VLSI Design Reliability― Noise in Digital Integrated Circuits V DD v(t) i(t) (a) Inductive coupling(b) Capacitive coupling (c) Power and ground noise

47. EE414 VLSI Design DC Operation Voltage Transfer Characteristic V(x) V(y) V OH V OL V M V OH V OL f V(y)=V(x) Switching Threshold Nominal Voltage Levels VOH = f(VOL) VOL = f(VOH) VM = f(VM)

48. EE414 VLSI Design Mapping between analog and digital signals

49. EE414 VLSI Design Definition of Noise Margins Noise margin high Noise margin low V IH V IL Undefined Region "1" "0" V OH V OL NM H L Gate Output Gate Input

50. EE414 VLSI Design Noise Budget l Allocates gross noise margin to expected sources of noise l Sources: supply noise, cross talk, interference, offset l Differentiate between fixed and proportional noise sources

51. EE414 VLSI Design Key Reliability Properties l Absolute noise margin values are deceptive »a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) l Noise immunity is the more important metric – the capability to suppress noise sources l Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver;

52. EE414 VLSI Design Regenerative Property Regenerative Non-Regenerative

53. EE414 VLSI Design Regenerative Property

54. EE414 VLSI Design Fan-in and Fan-out

55. EE414 VLSI Design The Ideal Gate V in V out g=  R i =  R o = 0 Fanout =  NM H = NM L = V DD /2

56. EE414 VLSI Design An Old-time Inverter

57. EE414 VLSI Design Delay Definitions t V out t V in 50% 10% 90% t pLH t pHL trtr tftf

58. EE414 VLSI Design Ring Oscillator

59. EE414 VLSI Design A First-Order RC Network v out v in C R t p = ln (2)  = 0.69 RC Important model – matches delay of inverter

60. EE414 VLSI Design Power Dissipation Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power:

61. EE414 VLSI Design Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av  t p Energy-Delay Product (EDP) = quality metric of gate = E  t p

62. EE414 VLSI Design A First-Order RC Network v out v in CLCL R

63. EE414 VLSI Design Summary l Digital integrated circuits have come a long way and still have quite some potential left for the coming decades l Some interesting challenges ahead »Getting a clear perspective on the challenges and potential solutions is the purpose of this book l Understanding the design metrics that govern digital design is crucial »Cost, reliability, speed, power and energy dissipation