Altera Technical Solutions Seminar 2000. Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration.

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Presentation transcript:

Altera Technical Solutions Seminar 2000

Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap Quartus Demo

Agenda Introduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration Intellectual Property Design Iteration Design Optimization Internet Interface Roadmap u Incremental Compilation u SignalTap™ Logic Analysis u SameFrame™ Pin-Out

Easy-to-Use Verification Tools  Integrated HDL Simulator for Verifying Code Before Compilation  Integrated Gate-Level and Timing-Level Simulation  Nodes Automatically Located in Source Code  Easy Integration with Third-Party Verification Tools

Project Root AB DE GH C F HDL Simulator Compiler Timing & Board Verification Incremental Recompilation

SignalTap™ Logic Analysis APEX Embedded Logic Analysis Communication Cable Quartus

Debugging Internal Logic Embedded Logic Analyzer CPUDesignBlock DesignBlockPCI

Embedded Logic Analyzer  Parameterized Megafunction  Integrated with Quartus Signal Selection Signal Selection Trigger Setup Trigger Setup Run Control Run Control Waveform Display Waveform Display  Operates at System Speed

Memory Usage ,0481, Channels Memory Depth - Samples Device EP20K100EP20K160EP20K200EP20K300EP20K400EP20K600EP20K1000 ESBs

SignalTap Plus

SignalTap Plus System Analyzer JTAG Internal Chip-level Activity External Board-level Activity System Centric Debug MasterBlaster Communications Cable

SignalTap Plus Specifications  All MasterBlaster capabilities Plus:  32 channel logic analyzer 1 external clock input 1 trigger output  1M samples per channel  Sample Rate Synchronous MHz (external clock) Asynchronous MHz (internal clock)

SignalTap Plus Specifications  Triggering 4 level sequence Event count (1k occurrences) Pattern duration (1k clocks) Timeout (16M clocks)

Industry Comparison Agilent (HP) LogicWave

APEX 20K SameFrame Support 196-Pin FineLine BGA Device EP20K100EP20K200EP20K Pin FineLine BGA 484-Pin FineLine BGA 672-Pin FineLine BGA

APEX 20KE SameFrame Support 196-Pin FineLine BGA Device EP20K100EEP20K160EEP20K200EEP20K300EEP20K400EEP20K600EEP20K1000E 324-Pin FineLine BGA 400-Pin FineLine BGA 484-Pin FineLine BGA 672-Pin FineLine BGA 900-Pin FineLine BGA

Design Iteration Summary  Verify Behavior Before Compiling  Incremental Compilation Speeds Time to Market Changes Made Quickly Changes Made Quickly Compilation Only Performed on Changed Portions of Design Compilation Only Performed on Changed Portions of Design More Opportunity to Optimize More Opportunity to Optimize  SignalTap/Plus for Real-Time Hardware Debug  SameFrame Pin-Out for Density, Package Changes

SOPC Development Board Overview  Complete Hardware Platform for SOPC Design System resources for microprocessor, memory, custom logic, & standard I/Os System resources for microprocessor, memory, custom logic, & standard I/Os  Order code: SOPC- BOARD/A4E APEX 20K400E 652–1 APEX 20K400E 652–1 Now ships with –1 or –2X Now ships with –1 or –2X Plan to ship with –1X when available Plan to ship with –1X when available Future upgradeable to 20K Future upgradeable to 20K Shipping now!

Key Feature Overview General Purpose Memory EPC2EJTAG JTAG MasterBlaster Configuration VGA LCD 16 x 2 Ch LEDSwitches Display/Switches SRAM DIMM Socket PMC Mezazanine Connector SRAM Bank-1 256K x 32 High-speed Cache Memory SRAM Bank-1 256K x 32 EPROM SDRAM 4M x 64 Flash Logic Analyzer Connector Pins General Purpose Connectors Configuration IEEE 1284 Parallel I/O Serial I/O USB Ethernet MII IEEE 1394A PS2/ mouse/ keybrd RS232

Product Overview  SOPC Development Board product ships with: SOPC Board SOPC Board MasterBlaster™ MasterBlaster™ CD ROM CD ROM User Guide User Guide Test cores Test cores 99 IP Catalog 99 IP Catalog Link to web info Link to web info

Product Overview (continued)  Operates with Altera and AMPP IP  PCI development using PMC connector only Not in PCI form factor (standalone) Not in PCI form factor (standalone) APEX PCI board scheduled for 3Q00 APEX PCI board scheduled for 3Q00  Demonstration programming files (.pof) Posted on IP MegaStore site as available Posted on IP MegaStore site as available