Design TWG 2000 Update Plans for 2001 Hsinchu, Taiwan December 2000

Role of Design in ITRS uBefore 1999 –Focused on hardware design and test: tool issues and technologies –Detached from rest of Roadmap u1999 –Highlighted SOC trends and requirements –Better integration, interaction with other ITWGs u2001 and beyond –Much more involvement in crosscut issues with other ITWGs l E.g., panel on interconnect systems and optimization; chip size; cost;... l Bidirectional interactions with other ITWGs –Consideration of new and important areas: l Applications l Architectures l Optimized uses of process technology l Analog/mixed signal and other technologies –More quantitative data/metrics/cost issues

Functionality + Testability Functionality + Testability + Wire Delay Functionality + Testability + Wire Delay + Power Mgmt Functionality + Testability + Wire Delay + Power Mgmt +Embedded software Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging Functionality + Testability + Wire Delay + Power Mgmt +Embedded software + Signal Integrity + Hybrid Chips + RF + Packaging + Mgmt of Physical Limits 1 K 1 Billion # Transistors *Exponentially growing number of devices *Design complexity is exponential function of device count Superexponential Design Complexity

$150K / Staff Yr. (In 1997 Dollars) Potential Design Complexity and Designer Productivity ,000 10, ,000 1,000, , , ,000,000 Logic Tr./Chip Tr./S.M. Year Technology Chip Complexity Frequency Staff Staff Cost* nm 180 nm 130 nm 13 M Tr. 20 M Tr. 32 M Tr. 130 M Tr M 120 M 160 M 360 M Yr. Design x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Equivalent Added Complexity Design Productivity Crisis

The Need for Built-In Self-Test uChip boundary cannot support needed data volumes without increasing test time (20x - 100x!!)

Model for SOC Design (a reasonable scenario) uDesign effort = constant (small design team, short time to product) uNew design productivity (logic) : + 30%/yr u(Reuse design productivity) = (New design productivity) / 2 uChip size is up to 1 cm 2 uResult: up to 94 % of die occupied by memory, or smaller die

A Scenario for SoC Design Productivity

Scenario: major increase in SOC memory content forced by insufficient design, reuse productivity increases (Japan) ITRS meeting, San Francisco, 2000 A Scenario for SoC Design Productivity

SOC Low Power Total Power Trend with No Low Power Solution Total Power Trend with Low Power Solution Scenario to keep 3W ITRS, meeting in Leuven

Goal: Living Roadmap uTransparent, self-consistent Roadmap –Documentation of algorithmic relationships within, between different parts of the Roadmap –Some relationships or derivations inherently difficult to capture, e.g., Max Litho Field Size derivation -- but these can be hard-wired uSanity checks (e.g., cost or power), which rule does not belong checks, etc. uEasier calibration, adjustment to actual design or technology data points uInitial focus: ORTCs uInteractions with other ITWGs, panels (chip size, etc.)

Living Roadmap Framework u GSRC Technology Extrapolation (GTX) Engine u Open source, allows flexible capture and study of impact of modeling choices, optimization constraints

System Drivers (SoC) Chapter Proposal uProposal: Evolve from SoC Chapter in 1999 ITRS uRationale –SOC is too specific; ITRS should not perpetually contain such a chapter –Terms such as ASIC, MPU (with all their flavors) are not well-defined in the ITRS front material –Should set context: what is consuming the silicon? with as concrete definitions as possible (replace SoC chapter) uFour driver classes (proposed starting point) –Analog/RF/MEMS –ASIC = compiled HDL gates –High-volume custom = P, DSP, embedded memories, reprogrammable –SoC = high integration, low cost, low TTM uDesign, PIDS, Interconnect, Test, Packaging, other TWGs uUnder consideration by IRC

Design Chapter Organization - Proposal uFive areas of Design uDesign Process uInfrastructure, design process metrics, … uSystem-Level Design uDesigning the system uInfrastructure for design IP reuse uFunctional Verification uSystem-level, RT-level, … uLogical-Physical-Circuits uCircuits includes DSM effects, hard-IP reuse/migration, etc. uTest

Design ITWG Schedule (Tentative) uUS Design DTWG - initial draft responsibility uUS Design TWG (with Test representation) met November 5 uDesign ITWG - meeting December 12 IEDM uUS Design DTWG - teleconference December 13 uFirst drafts of new text - January 31 uMeeting (ITWG, DTWG) in February

Cross-TWG Representatives TestTim Cheng InterconnectDennis Sylvester Assembly & PackagingDennis Sylvester LithographyAndrew Kahng Global Interconnect WGPeter Bannon Chip Size WGAndrew Kahng Frequency/Power linesMark Horowitz Layout DensityRich Howard Pkg Pins/BallsSylvester/Kahng

The Roadmap Ahead... Heights to which technology can take us Slippery slope if were not careful

The votes have been counted. Again and again. Its time to start the transition to the 2001 ITRS. I support the rule of law ( Moores Law, that is). Lets count every dimple on the wafer (on selected chips).