PIDS: Poster Session 2002 ITRS Changes and 2003 ITRS Key Issues ITRS Open Meeting Dec. 5, 2002 Tokyo

Outline PIDS Scope 2002 changes 2003 key issues Focused discussion of logic: 2001 ITRS scaling

PIDS Scope PIDS = Process Integration, Devices, and Structures Deals with –Process integration and full process flows –MOSFET and passive devices and structures –Device physical and electrical characteristics and requirements –Reliability Subcategories –Memory and logic –RF and Mixed-signal devices –Reliability –Also includes Emerging Research Devices Section (new in 2001 ITRS)

Changes in 2002 PIDS Chapter Low Standby Power (LSTP) technology requirements: physical gate length scaling is slowed by one year compared to 2001 ITRS (see dark boxes, next two slides) –As a result, performance and power dissipation scaling are slowed –This more accurately reflects real LSTP technology scaling Other changes are relatively minor –Updates –Clearer explanations in the notes and wording Major changes, issues will be dealt with in 2003 ITRS

LSTP Changes for 2002: Near-term

LSTP Table Changes for 2002: Long-Term

Key PIDS Issues for 2003 ITRS Re-do model-based logic scaling –Re-examine, improve models: for example, add S/D capacitance to formula for –Re-evaluation of assumptions, requirements for high-performance and low-power logic, especially maximum gate leakage current limits for high-performance logic Begin to evaluate non-classical CMOS technology requirements With Design TWG –Review of model-based scaling from a circuit point of view –Re-evaluation of maximum gate leakage current limit for high- performance logic –Evaluation of static power dissipation issues for high-performance logic –Use of multi-V t, multi-T ox : multiple transistor types on a chip –Circuit design, architecture power conditioning techniques –Dynamic or electrically alterable V t

Key PIDS Issues for 2003 ITRS (cont) With FEP TWG –Parasitic R s,d modeling: PMOS and NMOS –Re-evaluation of maximum gate leakage current for high- performance logic –L eff process control requirements –Review of poly depletion requirements –SOI requirements –Begin to evaluate process and material requirements for non- classical CMOS Memory –Re-evaluation of DRAM scaling: half pitch, EOT, cell size, cell size a factor, number of bits per chip, word line voltage –NVM (flash and FeRAM): changes in scaling of half pitch, cell size and cell size factor Mixed signal –Re-evaluation of overall requirements –Isolation Reliability: expand technology requirements

Model-Based MOSFET Scaling Approach: 2001 ITRS Simple models capture essential MOSFET physics embedded in a spreadsheet –Initial choice of scaled MOSFET parameters is made –Using spreadsheet, MOSFET parameters are iteratively varied to meet ITRS targets High Performance: historical 17%/year performance increase Low Power: specific, low level of leakage current

Assumptions for All Logic Types All modeling is done for nominal devices, room T Models are simplified (spreadsheet-based), assume basic transistor functioning doesnt change –No dynamic Vt –S=85 mV/decade –EOT electrical = EOT nm/0.5nm 0.8 nm for poly gate, 0.5 nm for metal gate (in 2007 or beyond) –Log(I sd,leak )~-Vt/S Gate leakage and junction leakage are each less than I sd,leak for all temperatures –Id,sat~g m,eff (Vdd-Vt) –Cideal = ox/(EOT electrical ); Cgate = Cideal + Cparasitic – =(Cgate Vdd)/(Id,sat)= intrinsic transistor delay –Parasitic Rs,d is included (20-30% of Vdd/Id,sat = Ron) –PMOS is like NMOS, except PMOS Id,sat is 40-50% of NMOS Id,sat –S/D capacitance is ignored in calculating DIBL is ignored in calculating I sd,leak

Drivers for High-Performance and Low- Power Logic High performance chips (MPU, for example) –Driver: maximize chip speed maximize transistor performance Goal of ITRS scaling: 1/ increases at ~ 17% per year, historical rate –Must maximize I on –Consequently, I leak is relatively high Low power chips (mobile applications) –Driver: minimize chip power minimize I leak (to conserve battery power) Goal of ITRS scaling: specific, low level of I leak Consequently, 1/ is relatively reduced

Scaling of Leakage Current and 1/ I sd,leak, High Perf. I sd,leak, Low Power (LSTP) 1/, Low Power (LSTP) 1/, High Perf.

Key MOSFET Scaling Results High-performance logic –Average 17%/yr improvement in 1/ is attained –I sd,leak is very high, particularly for 2007 and beyond chip static power dissipation scaling is an issue Assumption: I gate I sd,leak uncomfortably large I gate Low-power logic (particularly LSTP) –Very low I sd,leak target is met I gate I sd,leak I gate is very low: difficult to meet this –1/ scales considerably slower than for high- performance

Difficult Transistor Scaling Issues Previously discussed scaling results involve high-level, idealized MOSFET physics –Assumption: highly scaled MOSFETs with required characteristics can be successfully fabricated All lateral and vertical MOSFET dimensions (EOT [gate dielectric equivalent oxide thickness], x j s, spacer width, etc.) are scaling down rapidly along with physical gate length (L g ) With scaling, increasing difficulty is expected in meeting transistor requirements –High gate leakage Direct tunneling increases rapidly as EOT is reduced –Poly depletion in gate electrode increased effective EOT, reduced I on –Scaling S/D extension: x j – s- high R series,s/d, reduced I on –Etc. Material and process solutions needed

Difficult Transistor Scaling Issues: Key Potential Solutions High gate leakage –Direct tunneling increases rapidly as EOT is reduced –Potential solution: high-k gate dielectric (2005, low power logic) Poly depletion in gate electrode increased effective EOT, reduced I on –Potential solution: metal gate electrode (2007 and beyond) Scaling S/D: x j – s- high R series,s/d, reduced I on –Potential solutions S/D extension: alternate annealing, doping (2007 and beyond) Deep S/D: raised S/D, alternate contacts (2007 and beyond)

2001 ITRS Projections Versus Simulations of Direct Tunneling Gate Leakage Current Density for LSTP Logic 1.E-07 Implementation of high K will likely be driven by LSTP in ~ E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E Year J gate (A/cm 2 ) EOT (nm) Simulated J gate, oxynitride Specified J gate, ITRS EOT Beyond this point, oxynitride too leaky; high K needed (Simulations courtesy of C. Osburn, NCSU and ITRS)

Limits of Scaling Planar, Bulk MOSFETs 65 nm tech. generation (2007) and beyond: increased difficulty in meeting all device requirements with classical planar, bulk CMOS (even with material and process solutions: high K, metal electrodes, ….) –Control of SCE –Impact of quantum effects and statistical variation –Impact of high substrate doping –Control of series S/D resistance (R series,s/d ) –Others Alternative device structures (non-classical CMOS) may be utilized: being pursued by industry in parallel with material and process solutions –Band engineered transistors improved transport/mobility –Ultra thin body SOI & Double gate SOI - Including FinFET and Vertical FETs

Band Engineered MOSFETs: Surface- channel Strained-Si MOSFET Structures Graded Layer 0.05 = x Drain p + n - Si 1-y Ge y y = y n + Si Substrate n + poly n Strained Si Source SiO p - Si 1-y Ge y Graded Layer y = 0.05 y = x p + Si Substrate n + poly p Strained Si Source Drain SiO 2 Gate n + n + high mo bility channels p - Relaxed Si 1-x Ge x 2 Gate n - Relaxed Si 1-x Ge x Strained Si 1-x Ge x Courtesy of J. Hoyt - MIT p + + Increased effective mobility, increased I on - Difficult integration issues: manufacturability - Compatibility with ultra-thin body SOI - Cost

Schematic Cross Sections of Non-Classical CMOS Devices Bulk MOSFET Ultra-Thin Body MOSFET Double-Gate SOI MOSFET Electron Current Flow Ultra-thin silicon body Top & bottom gates Vertical MOSFET Double gates Drain Source SiO 2

Simplified Views of FinFET Double-Gate Device T-J. King and C. Hu, UC/Berkeley Key advantage: relatively conventional processing, largely compatible with current techniques FinFET (one type of double-gate MOSFET) S G DS G D SiO 2 BOX Gate Drain Source Schematic Cross-Section Top View