Work in Progress --- Not for Publication 6 December Interconnect Working Group ITRS 2000 Lakeshore Hotel, Hsinchu, Taiwan, R.O.C. 6 December 2000 Christopher Case Douglas Yu

Work in Progress --- Not for Publication 6 December ITWG Regional Contributors Japan Shinichi Ogawa Riichirou Aoki Yuji Furumura Taiwan Chen-Hua Douglas Yu Calvin Hsueh US Robert Geffken Christopher Case Europe Hans Joachim-Barth Gerhard Goltz Korea Hyeon-Deok Lee Hyunchul Sohn

Work in Progress --- Not for Publication 6 December Agenda Review of 1999 difficult challenges Key issues –Technology Requirements –Potential Solutions Updated tables 2001 preview Summary

Work in Progress --- Not for Publication 6 December Typical Chip Cross-section of Hierarchical Scaling Wire Via Global Intermediate Local Passivation Dielectric Etch Stop Layer Dielectric Diffusion Barrier Copper Conductor with Metal Barrier Liner Pre Metal Dielectric Tungsten Contact Plug

Work in Progress --- Not for Publication 6 December Difficult Challenges New materials Reliability Process integration Dimensional control Interconnect process with low/no device impact New materials and size effects Process integration Dimensional control Aspect ratios for fill and etch Solutions beyond copper and low <100 nm> 100 nm

Work in Progress --- Not for Publication 6 December Technology Requirement Issues Reliability requirements Usage of Optional Levels Planarization requirements Dielectric metrics including effective Is aggressive barrier thickness requirement (i.e. 0) needed for global wiring level - all 3 tables

Work in Progress --- Not for Publication 6 December MPU Near Term Years Constant reliability still requires improvement in defect density - based on 5 FITS and high performance MPU

Work in Progress --- Not for Publication 6 December MPU Near Term Years No significant dishing at local levels - thinning due to erosion over large areas (50% areal coverage)

Work in Progress --- Not for Publication 6 December MPU Near Term Years New combined dishing/erosion metric for global wire Cu thinning due to dishing for isolated lines/pads

Work in Progress --- Not for Publication 6 December MPU Near Term Years Expanded range of dielectric constants Return of bulk dielectric constant target specification

Work in Progress --- Not for Publication 6 December MPU Long Term Years Conductor effective resistivity relaxed along with barrier targets Similar changes proposed to SoC table

Work in Progress --- Not for Publication 6 December Typical Chip Cross-section of Hierarchical Scaling Wire Via Global Intermediate Local Passivation Dielectric Etch Stop Layer Dielectric Diffusion Barrier Copper Conductor with Metal Barrier Liner Pre Metal Dielectric Tungsten Contact Plug

Work in Progress --- Not for Publication 6 December Challenges High and ferroelectrics materials development Development and integration of ultra low materials with acceptable mechanical/thermal properties Fabricating low-temp low-loss SiO 2 optical interconnect Addressing turning radius of higher loss polymer optics Dielectric Potential Solutions Minor Corrections High and terminology for porous

Work in Progress --- Not for Publication 6 December Challenges Solutions for high A/R DRAM contacts Conformal barriers for dual damascene Cu - thin, effective diffusion barrier for low via resistance Barrier Potential Solutions Correction Addition of Atomic Layer Deposition

Work in Progress --- Not for Publication 6 December Barriers compatible with cooled conductors Challenges High A/R Al vias Nucleation layers other than TiN for high A/R DRAM contacts Advanced nucleation layers for Cu interconnect which do not degrade conductor effective resistivity Nucleation Potential Solutions Addition ECD Cu seed repair

Work in Progress --- Not for Publication 6 December Challenges Low temp CVD W for low compatibility High A/R contact fill for DRAM Cu fill of dual damascene structures with reduced CD and high A/R Identifying and implementing solutions after Cu and low Conductor Potential Solutions NO CHANGES

Work in Progress --- Not for Publication 6 December Challenges Continued development of tools/slurries/pads Cleaning technologies Many new low and high materials - may require new planarization approaches Pattern dependent planarization Planarization over passive elements for SOC Planarization Potential Solutions NO CHANGES

Work in Progress --- Not for Publication 6 December Challenges Dimensional control with small features and high A/R Selectivity to etch stops and hard masks Many new low and high materials - may require new chemistries Strip/clean compatibility with these new materials Low damage Etch Potential Solutions NO CHANGES

Work in Progress --- Not for Publication 6 December planning Interconnect needs to address novel devices especially vertical devices Performance impact of process induced variation Parametric performance models Can technology metrics be tied to performance limits –Trade-off between low and metal levels and design rules Include crosstalk metric

Work in Progress --- Not for Publication 6 December Rapid changes in materials Effect of increase of Cu resistivity at small line widths needs to be calculated Materials solutions alone cannot deliver performance - end of traditional scaling System level solutions must be accelerated Optical/rf/waveguide/3D current alternatives SoC implementations will propagate SoC may change competitive picture - driven by functionality not cost/area Last words