INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2

Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories  Processes

Chip Fabrication Steps  Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit.  In general, the steps can be grouped into two major parts:  Front-end-of-line (FEOL) processingFEOL covers everything (but not including the deposition of metal interconnect layers)  Back-end-of-line (BEOL) processingBEOL individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer

Processing In semiconductor device fabrication, the various processing steps fall into four general categories:  Deposition  Removal  Patterning  Modification of electrical properties

Processing (1/4) Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include  physical vapor deposition (PVD)  chemical vapor deposition (CVD)  electrochemical deposition (ECD)  molecular beam epitaxy (MBE)  atomic layer deposition (ALD)

Processing (2/4) Removal is any process that removes material from the wafer examples include etch processes (either wet or dry) and chemical-mechanical planarization (CMP).wetdryhemical-mechanical planarization

Processing (3/4) Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography For example, in conventional lithography, the wafer is coated with a chemical called a photoresist; then, a machine called a stepper focuses, aligns, and moves a mask, exposing select portions of the wafer below to short wavelength light; the exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.photoresiststepper mask plasma ashing

Processing (4/4) Modification of electrical properties has historically entailed doping transistor sources and drains (originally by diffusion furnaces and later by ion implantation). These doping processes are followed by furnace annealing or, in advanced devices, by rapid thermal annealing (RTA); annealing serves to activate the implanted dopants. Modern chips have up to eleven metal levels produced in over 300 sequenced processing steps.

Chip Fabrication Cycle

Processes  Oxidation  Diffusion  Ion Implantation  Deposition  Etching  Lithography All these processes are needed to build up different layers in a silicon structure

Oxidation of Silicon (Sio 2 ) Oxidation proceeds by the diffusion of an oxidant (molecular H 2 O or O 2 ) through the existing oxide to the Si/SiO 2 interface. The molecules react with Si to form SiO 2. Si (solid) + O 2 (vapor)  SiO 2 (solid) Dry Oxide Si (solid) + H 2 O (vapor)  SiO 2 (solid) + 2H 2 Wet Oxide Thermal Oxidation at  1000 o C o C

Oxidation of Silicon (Sio 2 ) The oxidation reaction occurs at the Si/SiO 2 interface. Therefore, as the oxide grows, silicon is consumed and the interface moves into the silicon. SiO 2 SiO 2 Surface Original Si Interface Silicon Substrate X0X0  0.5 X 0

Oxidation Equation x 0 = oxide thickness B = Parabolic Rate Constant x i = initial oxide thicknessB/A = Linear Rate Constant As temperature increases -A goes down -B goes up -B/A goes up X0X0 time Deal & Grove model: describes the growth kinetics of oxide films with thicknesses >300Å.

Oxidation Rates (Wet) Table 1. RATE CONSTANTS FOR WET OXIDATION OF SILICON OxidationAParabolic Rate Constant Linear rate constant temperature B B/A (°C) (  m) (  m 2 /hr) (  m/hr)

Oxidation Rates (Dry) Table 2. RATE CONSTANTS FOR DRY OXIDATION OF SILICON Oxidation AParabolic Rate Constant Linear rate constant temperature B B/A (°C) (  m) (  m 2 /hr) (  m/hr) We note that the values of both B and B/A for wet processes is much greater than for dry processes, leading to higher oxidation rates for the wet case.

Oxidation Example Problem: A silicon wafer has 0.5 micron thick layer of SiO 2. We now wish to grow additional oxide at 1100C in oxygen for 5 hrs. What is the final oxide thickness (x 0 )? Answer: From Table 2, A =.09, B =.027. x i = 0.5 micron. First calculate . This represents the equivalent time that we would have had to oxidize the wafer at 1100C to grow 0.5 micron. The final oxide thickness is calculated using the quadratic formula. = ( )/.027 = 10.9 hours =.027x( ) = x 0 = 0.5 [ ( X.429) 1/2 ] = 0.61 microns

Measurement of Oxide Thickness  The optical interference method is a simple technique to measure oxide thickness from <100Å to more than 1  m.  The method is based on the interference that occurs between light reflected from the air /SiO 2 interface and the Si/SiO 2 interface. Silicon SiO 2  light XoXo

Oxidation Furnace r Oxidation is carried out in a 3- zone resistance-heated furnace (1000 o C  0.1 o C). r The furnace consists of a quartz tube inside a ceramic sheath (heat diffuser). r The quartz tube is filled with oxidant gas in a laminar flow regime. r Inert gas is required for annealing.

Oxidation Charts r These are X o (oxide thickness in microns) vs. t(oxidation time) at different T (oxidation temperatures from say 700 to 1300 o C). Charts for dry, wet, or steam oxidation exist. r The thickness and time are drawn on log scales from 0.01  to 10  on the thickness axis and from 0.1 hr to 100 hr on the time axis. r Knowing the oxidation ambient (dry,wet,..), the oxidation temperature T, and the oxidation time t, we can read X o directly.

Oxidation Charts (Dry) r If the initial oxide thickness is zero, reading the value of X o is a direct matter.

Oxidation Charts (Wet)

Oxidation Example By Charts Problem: A silicon wafer has 0.5 micron thick layer of SiO 2. We now wish to grow additional oxide at 1100C in oxygen for 5 hrs. What is the final oxide thickness (x 0 )? Answer: For an initial oxide thickness exists 1- find the corresponding oxidation time (t oi ) at the oxidation temperature. 12 hrs 2- add the actual oxidation time (t) = 17 hrs 3- read the oxide thickness at time (t+t oi ). 0.6 µm r Remember to add times not thickness'!.

Many thanks to Prof. Hany Fikry and Prof Wael Fikry for their useful materials that help me to prepare this presentation. Thanks