Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Spezielle Anwendungen des VLSI – Entwurfs Special applications of VLSI design Prof. Dirk Timmermann, Claas Cornelius, Stephan Kubisch, Frank Sill, and Harald Widiger Course and contest

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Rules Attend all meetings Execute all tasks in given time Document your activities and results Presentations (5 min!) in English All slides have to be sent to Frank Sill 1 day before presentation

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Goal – Group ET/ITTI Given: Simple description of 16x16 bit multiplier in VHDL Task: Modification of VHDL description so that no multiplier symbol (*) will be used Multiplication in multiple clock cycles Synthesis for XILINX FPGA and UMC18 Layout in UMC18 technology Optimization for frequency * 1/energy (energy per clock cycle)

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Goal – Group CE Given: VHDL modules of two adders Task: Creation of 16x16 bit multiplier, which applies at least on of the given adders Multiplication in one clock cycle Synthesis for XILINX FPGA and UMC18 Layout in UMC18 technology Optimization for frequency

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Tools for the design flow Development of VHDL description with Mentor tools (tutor: Widiger) Intermediate step: Synthesis for FPGA with Xilinx tools (tutor: Widiger) Synthesis for UMC18 with Synopsys Design Compiler (tutors: Kubisch/Sill) Layout with Cadence Silicon Encounter (tutors: Sill/Cornelius) Illustration of power dissipation with Cadence Power Analyzer (tutor: Sill)

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Presentations Hard interrupt after 5 min by clock (after 4 min, a sign that 1 min is left) We want to know: –Which problems did you have? (with the design, not with tools) –How did you solve the problems? –Why do you prefer your chosen solutions? Language: English (content is much more important than your English abilities)

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Time table I – Work steps April, 6 th April, 27 th June, 1 st July, 6 th 3 weeks 2 weeks Publishing of design: 16x16bit Multiplier Part 1:Development of VHDL description Report part 1:Results for frequency, energy of gate level description (Xilinx-tools) Part 2:Synthesis for UMC 18 and Optimization for frequency, energy Intermediate meeting: Presentation of possible optimizations, intermediate results Part 2 contd:Continuation of optimizations Report part 2: Netlist for UMC18; results for frequency, energy from Synopsys tools Part 3:Layout with Silicon Encounter Report Part 3:Results for frequency, energy from Cadence tools Part 4:Use of all given possibilities for optimization of one criteria Final meeting: Picture of layout; picture from Cadence Power-Analyzer; results for frequency, energy 3 weeks June, 22 nd May, 18 th 2 weeks

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Time table II – Presentations Publishing of design: 16x16bit Multiplier Report part 1: 5 minutes, max. 5 slides, presentation of used multiplier parameter, characteristics, comparison values Intermediate meeting: 5 minutes, max. 5 slides, presentation of possible optimizations, results of part 2 Part 2: Report part 2: 5 minutes, max. 5 slides, report of 2nd part, used synthesis strategy, parameter, basic data of netlist, comparison values Part 3: Report Part 3:5 minutes, max. 5 slides, report of 3rd part, layout steps, parameter, comparison values Part 4: Final meeting: 5 minutes, max. 5 slides, report of all parts, characteristics, proceeding, comparison values, picture of layout and power dissipation April, 6 th April, 27 th June, 1 st July, 6 th 3 weeks 2 weeks 3 weeks June, 22 nd May, 18 th 2 weeks

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Time table III – short Publishing of design : 16x16 bit multiplier Contest test run – Xilinx FPGA (only ET/ITTI) Frequency & Energy Contest test run – UMC 18 Synthesis ET/ITTI: Frequency * 1 / Energy CE: Frequency Contest finals – UMC 18 Layout: ET/ITTI: Frequency * 1 / Energy CE: Frequency Final dinner with all attendees both top scorers are invited to one dish of their choice! April, 6 th April, 27 th June, 1 st July, 6 th 3 weeks 5 weeks

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Attendees ET/ITTI: Computational Engineering: