1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Martin Kittel

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Results Phase 2 Unique CSA-Tree for each Coefficient Ripple-Carry-Adder 3 Pipelines values for FGPA Area A (# of pairs)1336 frequency f133,636 MHz E avg 0.2499477 metric8,63 [s]

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Improvements Multiplier: No Changes Adder: Ripple Carry adder replaced by Sklansky adder Pipeline: Increased pipeline depth by 1

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Sklansky adder Halfadder:BK Cell: ABS 00K 01P 10P 11G I1I2S KKK KPK KGK PKK PPP PGG GKG GPG GGG

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Sklansky adder

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Optimizing design Now: high speed is possible: Lower frequency -> better Metric o.O values for ASIC P leak 2,55 uW frequency f1200 MHz E avg 0.2499478 metric1,367E-12 values for ASIC P leak 3,7 uW frequency f1600 MHz E avg 0.2499478 metric1,494E-12

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Final Result New approach – slow design: values for ASIC P leak 153.6679 nW frequency f244 MHz E avg 0.2499478 metric4.069E-13

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 ToDo phase 4 with same metric: drop pipelines use Ripple Carry adders with new metric with more interest in speed: parallelism improve adders

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Thank you for your attention!