1. Elevator Controller Simulation Using Spartan-3 FPGA for 4 floors, 3 cars
Yu Du, Yu Long
Electrical & Computer Engineering
University of Tennessee
This is the proposal for ECE551 project by Yu Du and Yu Long.

2. System Requirements Spartan-3 Starter Kit Board VHDL programming
Xilinx ISE Tools
Mentor Graphics/Synplicity tools
Using the Spartan-3 Starter Kit Board to simulate the actual elevator control. The source codes are programmed in VHDL. Mentor Graphics/Synplicity tools are used to capture, simulate and synthesize the design. A testbench with assert and report function will be generated for the verification of each module. The final P&R will be implemented in Spartan-3 FPGA board.

3. System Description 1st Floor, button “UP”
2nd Floor, button “UP”, “DOWN”
3rd Floor, button “UP”, “DOWN”
4th Floor, button “DOWN”
Each floor has car select button “1”, “2”, “3”
Inside each car has floor select button “1”, “2”, “3”,“4”
To simulate the actual elevator function, we need to implement the above button selection on the board. However, if we want to assign each function a physical button on board, there would not be enough input buttons for this project. The only possible solution is to combine car select and each car’s floor select button such that when a car selected, the floor select button is dedicated to that car.

4. System Description Inside the elevator: Outside the elevator:
Inside the elevator: SW<7,6> -> select cars: 00 car1; 01 car2; 10 car3; (11 car4)
BTN<3:0> -> select floor: BTN0: 1st floor; BTN1: 2nd floor; BTN2: 3rd floor; BTN3: 4th floor
Outside the elevator: 1st floor -> SW<0>: UP
2nd floor -> SW<1>: DOWN, SW<2>: UP
3rd floor -> SW<3>: DOWN, SW<4>: UP
4thfloor -> SW<5>: DOWN
Inside the elevator:
SW<7,6>
BTN<3:0>
Outside the elevator:
SW<5:0>

5. System Description Car Status Indicator: LD<2:0>
Car Status Indicator: Blinking, car is running; Off, car is ready.
LD<0> -> car1
LD<1> -> car2
LD<2> -> car3
Car Position Indicator: AN<0> -> car1
AN<1> -> car2
AN<2> -> car3
Car Status Indicator:
LD<2:0>
Car Position Indicator:
AN<2:0>

6. Design Schedule 10/28~11/10: VHDL coding
11/11~11/17: Synthesis, Simulation
11/18~11/25: Place and Routing, Post-layout Simulation
11/26~12/01: Implementation, Documentation
This is the schedule. We will try to keep up with the schedule.c

7. Design Assignment Input module with denouncing function
Output module with LED and LD display
Function module with timing, clock and FSM
BIST module with testbench
We will collaborate to see how we can best divide the whole work. First we need to implement one car function, then modify the design to add more cars.