1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design Jacob Maxa Results of Phase 5: Clock Issues 17.01.2013 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Clock Issues Why care about? Stretch wires to same length Same signal latency H-form tree

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Clock Issues Why care about? No ideal clock (slew rate ∞, no skew) Signal loose ideal form during transport Capacitive and resistive load Use distributed buffers for clock areas

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Clock Issues Why care about? Jitter Glitches Crosstalk

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Clock Network After cell placement Thicker wires to avoid electromigration and lower wire resistance Uses clock buffer Fill free spaces between cells Using clock mesh assistant in Encounter H-Tree from Double sided shield with GND net Avoid crosstalk and possible glitches Uses M3 & M4 layer to not interfere with signal wires in M1 & M2 Slide 5

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Results (3/3) Before Optimization After Optimization

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Slide 8 ASIC Layout Values Unitw/o clock netwith clock net Timing (T min / f Max )ps / MHz1769,9 / 565 Power (P dyn / P leak ) Clock Net Registers Combinational µW / nW % 1445,4 / 1190,8 0 73,56 26,44 2077,8/ 968,6486 22,36 57,68 19,96 Benchmark/MetricJ -2 1,8423*10 26 1,73663*10 26 Core Sizeµm 2 3269,448 Core Utilization%88,49190,799

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock End Thanks for your attention! Questions? Slide 9