1. Institut für Angewandte Mikroelektronik und Datentechnik Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock 23.06.2005 VLSI - Adder - Contest Final Report Results Optimization Tim Eickelberg

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design two Adders choosen for Optimization Decissions for last Phase KoggeStone - few levels for Carry-Generation (5) - faster than BrentKung (in literature) Brentkung - few Calculation Nodes in Tree-Structure - less Components than KoggeStone

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Optimizations of KoggeStone Adder Optimization Place Optimization Route why?Speed (ns) nothing base for evaluation1,55 Timing_Drivennothingcritical paths first1,58 Optimize_Timingnothingget best speed result1,55 nothingoptimize wire length shorter wires = faster1,53 Power_Drivennothingslower, but better for Low Power 1,64 Netlist from Synopsys: 0,96 ns first Step: minimize Area till best delay, so far: 865/865 delay: 1,47ns choose IO to Core Distance: 860/860 for better optimization possibilities

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design new Netlist for BrentKung Adder from Synopsys: 0.97 ns minimze Area IO to Core DistanceSpeed (without any optimization) (ns) 860/8601,46 870/8701,40 875/8751,49 872/8721,45 868/8681,42 869/8691,43 880/8801,42 882/8821,40

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Final Results: (including clk-tree generation for better rising edges of clk signal) BrentKung (882/882): Delay:1,326 nsFrequency:754,15 MHz Power:289,5 µW total@50Mhz19,2 µW total 240,4 µW Cell15,94 µW Cell 49,07 µW Net3,25 µW Net Area:1,896E10 nm² (or µm²) KoggeStone (875/875): Delay:1,353 nsFrequency:739,1 MHz Power:259,8 µW total@50Mhz17,58µW total 210,2 µW Cell14,2 µW Cell 49,6 µW Net3,3 µW Net Area:2,273E10 nm² (or µm²)

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design KoggeStone Photos

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design BrentKung Photos

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design List of all Values Value Name of design Best frequency :754,15MHzbrentkung097_final Best area: 1,896E4µm²brentkung097_final Best power@50MHz 17,58µWkoggestone096_final Best PDP 351,51fJkoggestone096_final Name of designer: Tim Eickelberg Name of Design max. delay [ns] max. frequency f max [MHz] Power Dissipatio n @ f max [µW] PDP [fJ] Core- Area [µm²] Power Dissipatio n @ 50 MHz [µW] brentkung097_final 1,326754,15289,5383,91,896E419,2 koggestone096_fin al 1,353739,1259,8351,512,273E417,58