Sequential Logic

Logic Styles Combinational circuits – Output determined solely by inputs – Can draw solely with left-to-right signal paths

Logic Styles Sequential circuits – Output determined by inputs AND previous outputs – Feedback loop

AB Circuit If A = 1 output must be 1 ABO

AB Circuit If A = 0 and B = 1 output must be 0 ABO

AB Circuit If A = 0 and B = 0 output may be 1 or 0 ABO 000/1??

AB Circuit Need to consider hidden input: ABLast Out Out x0 10x1 11x1

AB Circuit Describe next output O t+1 in terms of current output O t ABO t+1 00OtOt

Clocks Crystal Oscillators – Vibrate at known frequency when current applied – Used to generate clock signal:

Logisim Clock Clock alternates between high and low Button makes a nice manual clock

Hertz Frequency inverse of cycle time – Expressed in hertz. 1 Hz = 1 cycle per second 1 kilohertz (kHz) 1000 cycles/sec 1 megahertz (MHz) 1 million cycles/sec 1 gigahertz (GHz) 1 billion cycles/sec

Clocks Timing can be – Level-triggered : change can happen when clock high – Edge-triggered : change can happen on edge

Latches Latch : Level triggered memory

Flip Flops Flip Flop : edge triggered memory – Logisim won't reproduce

SR Circuit Set Reset circuit SRQ t+1 00QtQt undefined

Logisim To simulate SR need to add noise to delays

Logisim Oscillation : Circuit trapped in flip/flop – need to restart

Clocked SR Latch Level triggered based SR circuit SRQ t+1 00QtQt undefined

Clocked JK Latch JK makes SR safe – Prevent 1/1 from getting to SR - flips SRQ t+1 00QtQt

D Latch D Latch : Stores single bit during low clock DQ t

Memory's Atom Basic building block of memory

Logisim Built in D Flipflop – D – Clock – Preset (force 1) – Clear (force 0) – Enable (1 or floating is on)

Registers Register : Array of D Flip-flops

Registers Register : Write requires clock and write signal

Main Memory Big old matrix of flip flops

Main Memory 2-4 decoder logic picks memory address

Main Memory 3 bits wide

Implemeneted