Breaking the Cost Barrier 1 Low-Cost, High-Speed Programmable Solutions No Compromises

Breaking the Cost Barrier 2 Xilinx Breaks the Programmable Logic Cost Barrier  Device cost * 100K units, slowest speed, lowest density, cheapest package, mid-1999 Programmable logic is the most cost-effective logic solution!  Features  Performance In-system re-programmable FPGA RAM Boundary scan Low power >100 MHz FPGAs <$3* CPLDs near $1*

Breaking the Cost Barrier 3 Programmable Logic Reduces All Cost Factors  Development system  NRE  Learning time  Design time  Risk  Flexibility  Testing  Time-to-market Starts at $95 $0 Hours Hours to days Zero with Core solutions Low Reprogram (even over web) 100% factory tested Days to weeks

Breaking the Cost Barrier 4 Agenda: Breaking the Cost Barrier  Example design challenge - PC99 —solution alternatives  FireWire interface challenge —SpartanXL FPGA solution —Foundation software solution  SDRAM controller challenge —XC9500XL CPLD solution —Foundation and WebFITTER software

Breaking the Cost Barrier 5 High Volume, Cost Sensitive Challenges Are Met  Programmable solutions now meet high-volume needs —low cost —fast time-to-market  Example applications —consumer products —personal computers —PC peripherals  PC standards drive these applications —measure the solution against PC requirements

Breaking the Cost Barrier 6 Example Applications Digital audio mixing desks Web TVs Network computers Cell phones Video phones Security systems Process controllers Internet appliances Digital TV Set-top boxes Credit card readers Graphics acceleration DVD Hard drives Printers Voice processing Digital cameras Fax machines PCI USB Medical imaging Test equipment PC99 Satellite base stations Personal digital assistants GPS Automotive cabin controls Copiers PCS phones Network interface cards Modems Handsets I/O interface boards ADSL PC Peripherals SDRAM Controllers Gate array replacement Discrete logic integration Badge readers Arcade games DSP Ethernet adapters Compact PCI PCMCIA IIC Reconfigurable computing Flight simulators RAID ISDN Modems Video editing MPEG/JPEG Bar code readers Color correction Network routers Hubs PBX switches Fiber optics Click drives Video capture cards Video compression RISC interface Satellite decoders Robotics Mobile computing PCS ground stations Electronic toys Device bay Cable modems PC network cards Video cameras Home theatre Optical drives POS terminals CDROM drives Digitizers Imaging systems Telephony Audio Digital VHS Digital Hi-Fi DSS Digital monitors Card bus CAN bus Video conferencing LANs Network computers Music synthesizers Camcorders Household appliances FireWire Multimedia LCD projectors Monitors Docking stations Consumer electronics Personal electronics Handheld scanners Instrumentation Security systems HDTV VCR

Breaking the Cost Barrier 7 Programmable Logic Challenge PC99 Example  Intel/Microsoft guidelines for PCs built  Minimum 300 MHz processor, 32 MB RAM  Eliminates ISA bus —12 MHz USB ports for mouse, keyboard —400 Mbps FireWire ports for drives, audio, and video —Device Bay recommended for upgrading USB or FireWire peripherals without opening the box  Mobile PC requires small size, low power

Breaking the Cost Barrier 8 Xilinx Solution for PC99 in PCs and Peripherals Processor Personal Computer Peripherals SpartanXL USB interface/ FireWire interface SpartanXL USB interface/ FireWire interface Device Bay Memory XC9500XL SDRAM Controller USB, FireWire interfaces USBFireWire

Breaking the Cost Barrier 9 FPGAs and CPLDs Often Co-Exist in the Same System  FPGAs excel at: —higher density —pipelined logic —FIFOs, register files –using RAM  CPLDs excel at: —deterministic performance —fast pin-to-pin speed —state machines —wide decoding

Breaking the Cost Barrier 10 CPLDs FPGAs Xilinx Low-Cost Solutions Span the Density Range

Breaking the Cost Barrier 11 FPGA Challenge FireWire Example  FireWire part of PC99 spec is used to demonstrate the benefits of Xilinx FPGAs  IEEE 1394 standard —based on Apple’s original definition of FireWire  High speed serial bus —400 Mbits/s required for PC99; increasing to 3.2 Gbits/s  For emerging consumer electronics —digital camcorders, DVD players, digital VCRs, HDTV, set-top boxes, video conferencing  For traditional PC peripherals —hard drives, printers, scanners, modems

Breaking the Cost Barrier 12 Physical Layer Physical Layer 400 MHz FireWire Receive 50 MHz Link Layer Interface FireWire Link Layer Interface Transmit Section Transmit 8 Application Interface CRC Cycle Start Core State Machine FIFOs Request/ Data PHY Interface  Physical layer operates at full 400 MHz data transfer rate —serial-to-parallel conversion drops data rate to 50 MHz for back-end link layer  Link Layer includes CRC generation and FIFOs

Breaking the Cost Barrier 13 Challenges Facing the Design Engineer Design complexity Flexibility for an evolving standard Design cycle time HDL entry Cost control High performance FIFOs Design time Design tools Low power

Breaking the Cost Barrier 14 Potential Solutions  Discrete logic —not practical approach any longer —few available 3.3V/2.5V devices available  Chip sets —few available —expensive  Custom ASIC —long design cycle —costly to rework  Programmable Logic

Breaking the Cost Barrier 15 Spartan Series FPGAs Provide Solution Reprogrammable: instant updates Flexibility and design complexity —feature-rich programmable architecture High performance: >100 MHz parallel logic Design tools —established, easy-to-use development tools —complete software support and extensive cores (IP) Cost control —advanced process technology for small, low cost die —streamlined manufacturing provides total cost management

Breaking the Cost Barrier 16 Xilinx FPGA Architecture Benefits  SRAM programming cells —easy design changes  On-chip distributed SelectRAM memory —efficient FIFOs  Segmented routing —high speed and low power  Dedicated carry logic —high speed counters and arithmetic

Breaking the Cost Barrier 17 Reprogrammability  Fast time to market —immediate design changes —no cost penalty for mistakes and updates  Immediate production —no conversion costs —off-the-shelf —no inventory risk  100% tested —streamlined Xilinx testing reduces costs

Breaking the Cost Barrier 18 High Performance FIFOs Using SelectRAM Memory  Any logic block can be used as SelectRAM memory  Distributed RAM provides high performance solutions  Features —synchronous write, asynchronous read —separate read port in dual-port mode for FIFOs

Breaking the Cost Barrier 19 2 bits 32 bits A0 A1 A2 A3 A4 O1 DQ DQ Q1 Q2 CLB D1 D2 WE CLK D1 Logic CLB RAM Provides 16x the Storage of Flip-Flops  Configurable Logic Block (CLB) storage: —SelectRAM: 32 bits per CLB —flip-flops: 2 bits per CLB  CLBs in SpartanXL series

Breaking the Cost Barrier 20  Short interconnect segments are combined to create custom routing paths automatically  Minimizes capacitance —higher speed & lower power  Internal three-state buffers for integrated buses  Dedicated clock routing for high speed and low skew High Speed & Low Power Through Segmented Routing CLB Long Lines General Purpose Switch Matrix Switch Matrix

Breaking the Cost Barrier 21  All Xilinx FPGAs minimize power by using segmented interconnect  3.3V SpartanXL FPGAs consume less than half the power of 5V Spartan FPGAs  Power Down mode reduces quiescent current to 100  A SpartanXL Low Power Spartan Spartan XL Power Down

Breaking the Cost Barrier 22 Fast Arithmetic and Counters  Increased arithmetic density and speed —dedicated carry logic in CLBs —dedicated carry routing —16 bits at 120 MHz  DSP functions more efficient in FPGAs than dedicated DSP processors —twice the speed —one-tenth the cost CLB carrycarry carrycarry

Breaking the Cost Barrier 23 SpartanXL 3.3-V Series No Compromises

Breaking the Cost Barrier 24 SpartanXL Implementation  Implement FIFO part of FireWire design as an example  50 MHz required

Breaking the Cost Barrier 25 Equations/ Schematic; Single designer Timing- Driven Place and Route VHDL or Verilog Synthesis; Single designer HDL Back Annotation Synthesis and Cores; Small team Tighter ties with synthesis vendors Cores, HDL, Design reuse, Behavioral compiler; Larger design teams Module Compile Module Guide Evolution of Programmable Logic Tools Xilinx Design Tools Support Your Methodologies TIMELINE Future Evolution of Programmable Logic Design

Breaking the Cost Barrier 26  Ready-to-Use  Push-button, high- performance design  Mixed-level design —easy schematic entry —superior HDL solution  Low-cost Base system supports all SpartanXL and XC9500XL devices Xilinx Foundation Series

Breaking the Cost Barrier 27 Instant Productivity  Intuitive GUIs, with design wizards  Mixed-level, mixed- language design environment  Push-button design flows  Intuitive project management Demo

Breaking the Cost Barrier 28 Best-in-Class EDA Technology Synopsys Synthesis Xilinx Implementation tools (including A.K.A. Speed Technology) Aldec Design Entry Tools Optional RTL HDL Simulation Aldec Gate-Level Simulator K-Paths Enhanced Static Timing Analyzer Demo

Breaking the Cost Barrier 29 Unified Design Environment Design File Management Window with File, and Version Tabs Foundation Flow Engine Window with Content, and Report Tab Standard Windows Pull-down Menus Console Window with Error, Warning, and Messages Tabs Standard Windows Tool Bar Status Indicator Flow Button Demo

Breaking the Cost Barrier 30  On-line help includes link to support.xilinx.com —dedicated support web site —result of Silicon Xpresso initiative Foundation On-Line Help Demo

Breaking the Cost Barrier 31 Graphical State Editor Language Assistant Graphical State Editor Language Assistant Superior HDL Solution Design Creation  VHDL & Verilog HDL Design Capabilities Including: —graphical state diagram editor —powerful HDL editor with integrated language assistant —LogiBLOX and CORE Generator instantiations  HDL tutorials from Esperan  Xilinx Verilog CBT course Demo

Breaking the Cost Barrier 32 Design Wizard automates the process of adding an HDL symbol into a schematic. HDL Design becomes as easy as schematic entry with drop in blocks of HDL. HDL Editor directly associated with new schematic object Mixed-Level Design HDL Design becomes as easy as schematic entry with drop in blocks of HDL. HDL editor directly associated with new schematic object. HDL Design becomes as easy as schematic entry with drop in blocks of HDL. HDL editor directly associated with new schematic object. Demo

Breaking the Cost Barrier 33 X X Foundation “Pull Automation” runs both Synthesis and Implementation tools after the push of a single button and completion of the synthesis / implementation dialog. Optional HDL constraint entry and TimeTracker GUIs illustrate estimates of your design’s critical paths using an intuitive spreadsheet format or Push-Button Synthesis Demo

Breaking the Cost Barrier 34 Push-Button Performance  Xilinx A.K.A. Speed technology —high quality of results —short run time Demo

Breaking the Cost Barrier 35 Design Results All constraints were met. Timing summary: Timing errors: 0 Score: 0 Constraints cover 1649 paths, 94 nets, and 516 connections (100.0% coverage) Design statistics: Minimum period: ns (Maximum frequency: MHz) Demo

Breaking the Cost Barrier 36 Beyond Push-Button Implementation  FPGAs allow for extensive optimization through creative design and implementation  Standard library counter runs at 120 MHz in SpartanXL using default options  Asynchronous frequency counter runs at over 400 MHz! —Uses extensive pre-scaling

Breaking the Cost Barrier 37 AllianceCORE Solutions  Core solutions leverage the optimization and verification of third parties  FireWire AllianceCORE design and evaluation board available from Integrated Intellectual Property  Fully tested and verified for Xilinx FPGAs —pennies per chip in volume Application Interface CRC Cycle Start Register Set CRC Check Core State Machine FIFOs Request/ Data PHY Interface Data Status Packet Analyzer

Breaking the Cost Barrier 38 Free Software & Free Cores Included (Cores offer over 1,000,000 permutations!) Data sheets CoreLINX: Web Mechanism to Download New Cores SystemLINX: Third Party System Tools Directly Linked With Core Generator Parameterized Cores Core Generator Delivery System Core Generator Delivery System Demo

Breaking the Cost Barrier 39 PCI32 Spartan - Lowest Cost PCI Standard Chip External PLD 7K Gates 7K Gates Logic Component cost 100K units Standard Chip PCI Master I/F XCS20XL-4 TQ144* Solution <$7 PCI Master I/F * Supported devices: XCS20XL XCS30XL XCS40XL Power by $5 $20 $10 $15

Breaking the Cost Barrier 40 High-Value Applications with Spartan *Prices are for 100K units, plastic package

Breaking the Cost Barrier 41 SpartanXL Benefits  Fast time-to-market —user programmable  Low cost  Features for complex logic —high speed —low power  Easy to use —fully supported by Xilinx and third-party software

Breaking the Cost Barrier 42 CPLD Solution for PC99 SDRAM Controller Example Processor Personal Computer SpartanXL USB interface/ FireWire interface SpartanXL USB interface/ FireWire interface Device Bay Memory XC9500XL SDRAM Controller USB, FireWire interfaces USBFireWire

Breaking the Cost Barrier 43 Challenges Facing the Design Engineer 100 MHz minimum speed Multiple SDRAM protocols Sufficient address width Clock flexibility Resources for future expansion Small package HDL entry Cost control Minimal programming overhead Board layout before design is complete Design time Three-state flexibility 3.3V/2.5V

Breaking the Cost Barrier 44 Memory Interface Block Diagram SDRAMs Clock Write Reset Address[23:0] Address[11:0] CS RAS CAS WE Data[15:0] Complete SDRAM Controller in a single CPLD Microprocessor CPLD SDRAM Controller

Breaking the Cost Barrier 45 SDRAM Interface Close-up Address[23:0] Data[15:0] ADDR[11:0] Clock Reset Write CS RAS CAS WE ADDR[23:12] ADDR[11:0] Refresh Counter Address Decode Chip Select Mode Register State Machine

Breaking the Cost Barrier V XC9500XL Solution  Optimized for 3.3-V systems —compatible levels with 5.0/2.5V —no power sequencing restrictions!  Meets performance requirements —high f MAX = 200 MHz —fast t PD = 4 ns  Best ISP/JTAG support in industry  Best pinlocking in industry  Advanced packaging - New CSPs !

Breaking the Cost Barrier 47 XC9500XL Architecture New extra-wide function block inputs

Breaking the Cost Barrier 48 XC9500XL Function Block  Handles SDRAM address width with 54 inputs —highest function block fan-in on fast CPLDs

Breaking the Cost Barrier 49 XC9500XL Macrocell Local macrocell clock inversion control Flexible clocking and three-state control

Breaking the Cost Barrier 50 XC9500XL Special System Designer Benefits  Input hysteresis  Fully compliant ISP/JTAG guarantees no ISP lock out  No power sequencing restrictions  Hot plug-in

Breaking the Cost Barrier 51 Advanced CSP Packaging Supports high-growth market segments: Communications, Computers, Consumer Uses standard IR techniques for mounting to PC board

Breaking the Cost Barrier 52 XC9500XL Solution Meets Design Challenges 3.3/2.5V electrical compatibility —no power-sequencing restriction Chip scale packaging Pin-locking allows design change flexibility No programmer necessary with JTAG-based programming Fast design time VHDL, Verilog or ABEL design entry

Breaking the Cost Barrier MHz minimum speed —133 MHz met Multiple SDRAM protocols —48% remaining capacity Sufficient address width (32 or 64 bit) Any clocking and three-state option needed Abundant resources for future expansion Low cost XC9500XL Solution Meets Design Challenges

Breaking the Cost Barrier 54 XC9500XL 3.3-V Family

Breaking the Cost Barrier 55 XC9500XL Design Software  XC9500XL fitters in all Xilinx standard software packages  Support for schematics, Verilog, VHDL, ABEL —Exemplar, Synopsys, Synplicity, and others  JTAG downloader for both FPGAs and CPLDs  WebFITTER simplifies test-driving CPLDs Demo

Breaking the Cost Barrier 56 Design in VHDL, Verilog, ABEL, etc. Submit design to WebFITTER Evaluate results Demo CPLD Design on the Web  No software to load —no user resources needed —no license  WebFITTER software always current —no upgrade CDs  Runs fast on network (minutes)

Breaking the Cost Barrier 57 WebFITTER Intro Page Demo

Breaking the Cost Barrier 58 WebFITTER Activity Report Demo

Breaking the Cost Barrier 59 WebFITTER Report File Demo

Breaking the Cost Barrier 60 SDRAM Controller Implementation in XC9500XL  Results for XC95144XL  Utilization —52% of capacity available for other logic  Speed —faster than required for 133 MHz clock  Lowest-cost solution  Compare to chip sets and other CPLDs Demo

Breaking the Cost Barrier 61 Simple & Fast Low-Cost CPLD Solutions  Isolates user from interface issues —critical signal timing —electrical interfacing —control signal sequencing (state machine design) Variances In Interfaces SDRAM (i.e. Bank vs. SIMM) Unique System Back-End

Breaking the Cost Barrier 62 New XC9500XV 2.5V Family XC9500XV9536XV9572XV95144XV95288XV Macrocells Usable Gates t PD (ns) 1H H f SYSTEM Packages44PC (34) (Max. User64VQ (36)64VQ (52) I/Os)100TQ (72)100TQ (81) 144TQ (117) 208PQ (168) BGA 256BG (168) CSPs 48CS (36) 144CS (117)

Breaking the Cost Barrier 63 Example Applications Digital audio mixing desks Web TVs Network computers Cell phones Video phones Security systems Process controllers Internet appliances Digital TV Set-top boxes Credit card readers Graphics acceleration DVD Hard drives Printers Voice processing Digital cameras Fax machines PCI USB Medical imaging Test equipment PC99 Satellite base stations Personal digital assistants GPS Automotive cabin controls Copiers PCS phones Network interface cards Modems Handsets I/O interface boards ADSL PC Peripherals SDRAM Controllers Gate array replacement Discrete logic integration Badge readers Arcade games DSP Ethernet adapters Compact PCI PCMCIA IIC Reconfigurable computing Flight simulators RAID ISDN Modems Video editing MPEG/JPEG Bar code readers Color correction Network routers Hubs PBX switches Fiber optics Click drives Video capture cards Video compression RISC interface Satellite decoders Robotics Mobile computing PCS ground stations Electronic toys Device bay Cable modems PC network cards Video cameras Home theatre Optical drives POS terminals CDROM drives Digitizers Imaging systems Telephony Audio Digital VHS Digital Hi-Fi DSS Digital monitors Card bus CAN bus Video conferencing LANs Network computers Music synthesizers Camcorders Household appliances FireWire Multimedia LCD projectors Monitors Docking stations Consumer electronics Personal electronics Handheld scanners Instrumentation Security systems HDTV VCR

Breaking the Cost Barrier 64 High-Volume FPGA Price Leadership 100k unit volume price projections New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics New Applications Set Top Box DVD Digital Camera PC Peripherals Consumer Electronics Density (System Gates) k 40k 100k 60k 25k 60k 200k 100k 10K Gates Per Dollar in 2002! $20 $10

Breaking the Cost Barrier 65 * Prices are based on 100ku+, slowest speed grade, lowest cost package CPLD Price Leadership No Compromises Flexible ISP t PD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25  Flash) in 1999 No Compromises Flexible ISP t PD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25  Flash) in 1999

Breaking the Cost Barrier 66 Solutions for Low-Cost, High-Volume Applications  Low cost programmable logic —SpartanXL FPGAs available —XC9500XL CPLDs available  High performance  System-level features  Ease of evaluation and design —WebFITTER, Foundation 1.5i software available