© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 2 Objectives After completing this module, you will be able to: List the steps of the Xilinx design process Implement and simulate an FPGA design by using default software options

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 3 Outline Overview ISE Foundation Summary Lab 1: Xilinx Tool Flow Demo

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 4 Translate Map Place & Route Xilinx Design Flow Plan & Budget HDL RTL Simulation Synthesize to create netlist Functional Simulation Attain Timing Closure Timing Simulation Implement Create Code/ Schematic Generate BIT File Configure FPGA

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 5 Design Entry Plan and budget Whichever method you use, you will need a tool to generate an EDIF or NGC netlist to bring into the Xilinx implementation tools – Popular synthesis tools include: Synplify, Precision, FPGA Compiler II, and XST Tools available to assist in design entry – Architecture Wizard, CORE Generator™ system, and StateCAD tools Simulate the design to ensure that it works as expected! Plan & BudgetCreate Code/ Schematic HDL RTL Simulation Synthesize to create netlist Functional Simulation... Create designs in HDL or Schematic

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 6 Synthesis After coding up your HDL code, you will need a tool to generate a netlist (NGC or EDIF) – Xilinx Synthesis Tool (XST) included – Support for Popular Third Party Synthesis tools: Synplify and Synplify Pro from Synplicity, and Precision from Mentor Graphics Generate a netlist file

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 7 Implementation Consists of three phases – Translate: Merge multiple design files into a single netlist – Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs) – Place & Route: Place components onto the chip, connect the components, and extract timing data into reports Access Xilinx reports and tools at each phase – Timing Analyzer, Floorplanner, FPGA Editor, XPower Translate Map Place & Route Implement Netlist Generated From Synthesis Process a netlist file

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 8 Configuration Once a design is implemented, you must create a file that the FPGA can understand – This file is called a bitstream: a BIT file (.bit extension) The BIT file can be downloaded – Directly into the FPGA Use a download cable such as Platform USB – To external memory device such as a Xilinx Platform Flash PROM Must first be converted into a PROM file Testing and Verification

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 9 Online Software Manuals See Development System Reference Guide for Flow Diagrams

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 10 Timing Closure

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 11 Outline Overview ISE Foundation Summary Lab 1: Xilinx Tool Flow Demo

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 12 ISE Project Navigator Enter Designs Access to synthesis tools – Including third-party synthesis tools Implement your design with a simple double-click – Fine-tune with easy-to- access software options Download – Generate a bitstream – Configure FPGA using iMPACT Xilinx ISE Foundation is built around the Xilinx Design Flow

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 13 Entering Designs Source Wizard available to assist with design entry Select source type – Design Entry Methods Schematic HDL source (VHDL and Verilog) – Design Entry Tools Architecture Wizard BMM/MEM/UCF Files Core Generator ChipScope Embedded Processor System Generator – Simulation Test Bench VHDL Verilog

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 14 Synthesizing Designs Double-click to Synthesize Generate a netlist file using XST (Xilinx Synthesis Technology) Highlight HDL Sources 1 2 Synthesis Processes and Analysis – Access report – View Schematics (RTL or Technology) – Check Syntax – Generate Post-Synthesis Simulation Model

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 15 Implementing Designs Implement a design – Translate Access reports Post-Translate Simulation Model – Map Access reports Post-Map Static Timing Manually place components Post-Map Simulation Model – Place & Route Access reports Analyze timing/Floorplan (PlanAhead) Manually place & route components And more Process netlist generated from synthesis Highlight HDL Sources 1 Double-click to Implement 2

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 16 The Design Summary Displays Design Data Quick View of Reports, Constraints Project Status Device Utilization Detailed Reports Design Properties Performance Summary (not shown)

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 17 Simulating Designs Verify the design with the ISE Simulator Select simulation 1 Highlight test bench 3 Double-click to simulate 4 Add a test bench – VHDL, Verilog, or Xilinx waveform file Perform a Behavioral Simulation – Use UNISIM/UniMacro library when FPGA primitives are instantiated in the design – Use XilinxCoreLib library when IP cores are instantiated in the design Perform a timing simulation – Use Xilinx SIMPRIM library when FPGA primitives are instantiated in the design SmartModels – Simulation library for both functional and timing simulation of Xilinx Hard-IP such as PPC, PCIe, GT, TEMAC are used in the design Select simulation type 2

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 18 Configuring FPGAs Configure FPGAs from computer – Use iMPACT to download bitstream from computer to FPGA via Xilinx download cable (ie. Platform USB) Configure FPGAs from External Memory – Xilinx Platform Flash Use iMPACT to generate PROM file and download to PROM using Xilinx download cable – Generic Parallel PROM Use iMPACT to generate PROM file - no support for programming – Compact Flash (Xilinx System ACE required) Use iMPACT to generate SysACE file - no support for programming Double-click to generate.bit 2 Highlight source file 1 Generate PROM files and download to devices using iMPACT Double-click to invoke iMPACT programming tools 3

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 19 Outline Overview ISE Summary Lab 1: Xilinx Tool Flow

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 20 Review Questions What are the phases of the Xilinx design flow? What are the components of implementation, and what happens at each step? What are two methods of programming an FPGA?

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 21 Answers What are the phases of the Xilinx design flow? – Plan and budget, create code or schematic, RTL simulation, synthesize, functional simulation, implement, timing closure, timing simulation, and BIT file creation What are the components of implementation, and what happens at each step? – Translate: merges multiple design files into one netlist – Map: groups logical symbols into physical components – Place & Route: places components onto the chip and connects them What are two methods of programming an FPGA? – Directly from Computer – From external memory device

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 22 Summary Implementation means more than Place & Route Xilinx provides a simple pushbutton tool to guide you through the Xilinx design process

© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only Tool Flow 23 Outline Overview ISE Summary Lab 1: Xilinx Tool Flow