1. This material exempt per Department of Commerce license exception TSU System Simulation

2. System Simulation 2 Objectives After completing this module, you will be able to: Describe the functionality of SimGen Describe the integration of SimGen within XPS Describe the simulation process Describe what SmartModel™ Libraries are and how to use them

3. System Simulation 3 Outline SimGen Simulation Procedure SmartModel Libraries

4. System Simulation 4 Simulation Generator Hardware Platform Generation Library Generation Embedded Software Development ISE Tools IP Library or User Repository MSS LibGen.a Compiler (GCC).o Linker (GCC) ELF MHS PlatGen Drivers, MDD MPD, PAO PCore HDL System and Wrapper VHD system.BMM Synthesis (XST) NGC NGDBuildUCF NGD MAP NCD, PCF PAR NCD BitGensystem.BIT BitInit download.BIT iMPACT system_BD.BMM SimGen Behavioral VHD Model SimGen Structural VHD Model SimGen Timing VHD Model Simulation IP ModelsISE Models Testbench Stimulus CompEDKLibCompXLib Application Source.c,.h,.s EDK Tool Flow download.CMD EDK SW Libraries

5. SimGen The Simulation Model Generation tool (SimGen) generates and configures various simulation models for the specified hardware SimGen will generate simulation models by using a Microprocessor Hardware Specification (MHS) file SimGen searches for input files in the following directories located in the project directory – /hdl/ system_name.[vhd|v] peripheral_wrapper.[vhd|v] – /implementation/ (if any of the peripherals are black-box) peripheral_wrapper.ngc system_name.ngc system_name.ncd

6. SimGen SimGen produces.[vh d|v] ***.[vhd|v].do _sim.bm m.sdf ** SimGen Generated Directories project_directorysimulation directory * * = behavioral/structural/timing **.sdf in timing simulation ***.[vhd\v] in behavioral or structural simulation

7. Memory Initialization To initialize memory in the simulation models created by SimGen, you need: – The compiled executable executable.elf – The simulation hardware model generated by executing SimGen system.vhd or system.v – The BMM file generated by PlatGen /implementation directory Data2MEM uses these files and generates a system_init.vhd file that contains block memory initialization content Data2MEM system_init.[vhd|v] system.bmm executable.elf system.[vhd|v]

8. System Simulation 8 Memory Initialization The system.bmm file is created by the PlatGen tool and carries block memory related information (see next slide) – Number of block memories – Address range for each set of block memory – Data indexing for each block memory in a set The executable.elf file is generated by the compiler and carries data variables and code The system.vhd file is generated by the SimGen tool and carries a hardware model of the system The Data2MEM program uses the above mentioned files, extracts data code information, and generates a system_init.vhd file that contains block memory initialization content

9. System Simulation 9 System.bmm File ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 [63:56] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 [55:48] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 [47:40] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 [39:32] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 [31:24] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 [23:16] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 [15:8] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram_if_cntlr_2_bram RAMB16 [0xffff0000:0xffff3fff] BUS_BLOCK plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_0 [63:56] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_1 [55:48] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_2 [47:40] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_3 [39:32] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_4 [31:24] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_5 [23:16] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_6 [15:8] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;

10. Simulation Libraries: XILINX UNISIM library – Used for behavioral simulation and contains default unit delays – Includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools SIMPRIM library – Used for structural and timing simulation – Includes all of the Xilinx Primitives Library components that are used by Xilinx implementation tools XilinxCoreLib library – Contains pre-optimized modules to take advantage of architectural resources – Library models are used for behavioral simulation – May be used for your own defined IPs Structural and timing simulation models generated by SimGen instantiate the SIMPRIM library components

11. Simulation Libraries: EDK EDK library – Used for behavioral simulation – Contains models of all the EDK IP components – PPC 405 processor models are not available for the ModelSim XE simulator – VHDL and Verilog support – Must be compiled for the target simulator – Compile the EDK library using GUI from XPS (see next slide) Library can also be compiled using the following command (Xilinx does not recommend) compedklib [ -h ] [ -o output-dir-name ] [ -lp repository-dir-name ] [ -X compxlib-output-dir-name ] [ -E compedklib-output-dir-name ]

12. System Simulation 12 Compiling Simulation Libraries With XPS project open: – Select Project  Project Options – Click the HDL and Simulation tab – In the Simulation Libraries Path area, select the EDK and Xilinx® libraries to compile – Click Compile If XPS project is not open: – Options  Compile Simulation Libraries

13. System Simulation 13 Outline SimGen Simulation Procedure SmartModel Libraries

14. Integration within XPS Invoke ise project using Project Navigator Add system_i.xmp as a source to the project Make sure that Sources view is set for Synthesis/Implementation Select system_i in Sources window and double-click Manage Processor Design to invoke XPS Start ISE and XPS 1

15. Integration within XPS Specify simulation parameters by selecting Project  Project Options – HDL and Simulation tab HDL Simulator Compile Script Simulation Libraries Path – EDK Library – XILINX Library Simulation Models Set up library paths using Project Options 2

16. Integration within XPS Generate the simulation models – Generation of simulation models: Simulation  Generate Simulation HDL Files Generate the Simulation Model 3

17. Use within the Project Navigator VHDL – Project  New Source  VHDL Testbench – Project  Add Source ; add the testbench to the project Verilog – Project  New Source  Verilog Test Fixture – Project  Add Source, add the testbench to the project Create/Add testbench file 4

18. Use within the Project Navigator VHDL – You must copy over the.do simulation file – Testbench.vhd must be added to the.do file – Testbench.vhd must include a configuration statement to load the RAM initialization strings included in _init.vhd Verilog – You must copy over the.do simulation file – Testbench.v must be added to the.do file – Testbench.v must include a #include statement to load the RAM initialization strings included in _init.v Alternatively, write your own.do script Copy.do files to the ProjNav directory Copy.do files to the ProjNav directory 5

19. System Simulation 19 Invoking ModelSim Simulator In Sources for window, select Behavioral Simulation view In Sources window, select testbench In Processes window, double- click on Simulate Behavioral Model Run ModelSim Simulator 6

20. System Simulation 20 Outline SimGen Simulation Procedure SmartModel Libraries

21. System Simulation 21 SmartModel Libraries SmartModel  Libraries are compiled simulation models that represent integrated circuits and system buses as black boxes. SmartModel Libraries: – Accept an input stimulus and respond with an appropriate output behavior – Provide improved performance over gate-level models – Protect proprietary designs – Can be used with any simulation tool that supports the SWIFT™ Interface

22. System Simulation 22 Creating SmartModel Libraries SmartModel  Libraries are compiled by using the VMC (Verilog Model Compiler) or the VhMC (VHDL Model Compiler) from Synopsys – Xilinx used VMC to compile a Verilog version of the PowerPC  processor and MGT – You do not need VMC or VhMC to use the Xilinx model Xilinx has compiled each model for a specific OS – Solaris™ Operating System, Windows®, Linux® VMC generates an object file that represents the Verilog file – Internal timing delays are maintained – It is an exact equivalent of the Verilog

23. System Simulation 23 Running a Simulation Using SmartModels The SWIFT interface provides access to SmartModel Libraries Changes required in the modelsim.ini: – Resolution = ps – Comment out the "PathSeparator" = / using “;” – Veriuser = $MODEL_TECH/libswiftpli.dll (SWIFT Interface) – Uncomment the following lines for the appropriate OS libsm = $MODEL_TECH/libsm.dll libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll set MODELSIM= \modelsim.ini Instantiate the appropriate MGT or PowerPC  processor primitive

24. System Simulation 24 Supported Simulators and Platforms Solaris Operating System (2.8, 2.9) – Mentor Graphics ModelSim SE simulator (6.0 and newer) – Cadence NC-Verilog simulator – Cadence Verilog-XL simulator – Synopsys VCS simulator Windows 2000 (SP2) or Windows XP – Mentor Graphics ModelSim SE simulator (6.0 and newer) Linux (7.2) – Mentor Graphics ModelSim SE simulator (6.0 and newer)

25. System Simulation 25 Solution Records 14597: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in NC-Verilog, Verilog-XL, and Synopsys VCS? 14019: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in ModelSim? 14181: Virtex-II Pro - What are the SWIFT Interface, Smart Model, VMC, and VhMC? What of these does Xilinx deliver? 14596: 6.1i SmartModels - What simulators support SmartModel simulation? 14365: Virtex-II Pro PowerPC - What is the difference between Bus Functional Model (BFM) and Smart Model (SWIFT interface) simulation?

26. System Simulation 26 Skills Check

27. System Simulation 27 Review Question Which three items are required to initialize memory in the simulation models created by SimGen?

28. System Simulation 28 Answer Which three items are required to initialize memory in the simulation models created by SimGen? – The compiled executable generated with the appropriate gcc compiler or assembler, from corresponding C or assembly source code – The simulation model generated by executing SimGen – The BMM file generated by PlatGen

29. Where Can I Learn More? Tool documentation – Getting Started with the Embedded Development Kit – Embedded System Tools Guide  Simulation Models Generator Support website – Xilinx Home Page: support.xilinx.com – EDK Home Page: support.xilinx.com/edk