1. 1 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 5: 9/7/2011 (VHDL to FPGA: A Tool Flow Overview ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

2. 2 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) MP1: Delayed released by this evening (9/7) HW1: Due Friday Midnight Announcements/Reminders

3. 3 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Common Questions

4. 4 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Common Questions

5. 5 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Common Questions

6. 6 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Common Questions

7. 7 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Introduction to mapping VHDL to FPGA hardware What you should learn –What are the major steps? –What is the basic purpose of each step? Overview

8. 8 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Input Hardware Description Langue (HDL) Synthesis Map Place & Route Hardware configuration file generation Major Steps

9. 9 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Graphical flow Implement Simulate Synthesize Map Place Route Download

10. 10 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Major Steps (Text: Chapters 13-20) Z <= (A and B) or C; Input VHDL description LUT A B C Z Transform primitive to technology dependent primitives (MAP) Z A B Transform VHDL into primitive gates (synthesis) C Associate primitive with specific Instances, and connect using Routing resources (PAR) LUT A B C Z Encode placement and routing description into a configuration file for programming a specific FPGA type 000 A B C 101 000 Z

11. 11 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) High Level Design Description VHDL Verilog C type languages (e.g. handle C) –Typically auto transformed into VHDL or Verilog Schematic capture (I believe ISE has this option) –Gate level (connecting structural components) –Statemachine bubble diagrams High level graphical –Simulink/System Generator (Xilninx) –Simulink/DSP Builder (Altera) http://www.youtube.com/watch?v=dSxqM7S2upA System on chip embedded system design –Xilinx EDK: http://www.youtube.com/watch?v=STGiqlBRVms http://www.youtube.com/watch?v=STGiqlBRVms –Altera SoPC:

12. 12 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Synthesis Application of Boolean logic theory Technology independent representation –EDIF (Electronic Design Interchange Format) Technology independent optimization –Combinational optimization 2-level Multi-level –Sequential optimization FSM state reduction retiming

13. 13 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) EDIF representation Gives a standard means to target a design to different vendors Example EDIF file –http://en.wikipedia.org/wiki/EDIFhttp://en.wikipedia.org/wiki/EDIF

14. 14 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Combinational Optimization This is a major area of active research! ABC from Berkeley provides and open source tool –http://www.eecs.berkeley.edu/~alanmi/abc/http://www.eecs.berkeley.edu/~alanmi/abc/ –This is a great starting place if you think you maybe interested in pursuing research in VLSI Computer Automation Design Tool development.

15. 15 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) MAP (Technology Mapping: Chapter 13) Translate device independent net list to device specific resources (for FPGAs a common device specific resource is a LUT) –Structural: Maintains structure –Functional: Will modify structure for optimization LUT A B C Z Z A B C

16. 16 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) PAR (Place and Route: Chapters 14-17) Place: Text Chapters 14 and 16 fundamentals Route: Text Chapter 17 fundamentals Tools and Challenge –VPR: http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html –Pathfinder –Open challenge (make some money?) http://www.eecg.toronto.edu/~vaughn/challenge/challenge.html

17. 17 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Place (Chapter 17) Bind each mapped resources to a physical device location –General Purpose Placing resources without knowledge of high level structure. Guided by local connection between resources –Structured Guided Makes assumptions about the structure of the circuit to guide placement. If circuit does not follow assumption will like give poor placement –User Guided Layout User provides guidance to the algorithm to help with placement Some way to provide this information –VHDL directives (e.g. relative location constraints RLOC) –GUI-based (e.g. Xilinx Floor Planner) Can help to remove critical paths, and greatly decrease tool running time

18. 18 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Route (Text: Chapter 17) Connect placed resources together Two requirements –Design must be completely routed –Routed design meets timing requirements Widely used algorithm “PathFinder” –PathFinder: A Negotiation-Based Performance- Driven Router for FPGAs PathFinder (FPGA’95) McMurchie and Ebeling –Reconfigurable Computing (Chapter 17) Scott Hauch, Andre Dehon (2008)

19. 19 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Place & Route: How hard is it? Let’s take a look at MP1’s layout

20. 20 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Configuration File Generation (Text: Chapter 19) Convert place & routed design into a device configuration file (e.g. bitfile for Xilinx devices) Download the configuration file to the FPGA

21. 21 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Next Class VHDL Review: State Machines

22. 22 - CPRE 583 (Reconfigurable Computing): VHDL to FPGA: A Tool Flow Overview Iowa State University (Ames) Questions/Comments/Concerns Write down –Main point of lecture –One thing that’s still not quite clear –If everything is clear, then give an example of how to apply something from lecture OR