Mid3 Revision Prof. Sin-Min Lee

2 Counters

3 Figure 9--1 A 2-bit asynchronous binary counter. Asynchronous Counter Operation

4 Figure 9--2 Timing diagram for the counter of Figure 9-1, output waveforms are shown in green.

5

6

7 Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle.

8 Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

9 Figure 9--5 Four-bit asynchronous binary counter and its timing diagram.

10 Figure A 2-bit synchronous binary counter. Synchronous Counter Operation

11 Figure Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).

12 Figure Timing diagram for the counter of Figure 9-11.

13 Figure A 3-bit synchronous binary counter.

14 Figure Timing diagram for the counter of Figure 9-14.

15

16 Figure General clocked sequential circuit. Design of Synchronous Counters

17 Figure State diagram for a 3-bit Gray code counter. Step 1: State Diagram

18 Step 2: Next-State Table

19 Step 3: Flip-Flop Transition Table

20 Figure Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8. Step 4: Karnaugh Maps

21 Figure Karnaugh maps for present-state J and K inputs. Step 5: Logic Expressions for Flip-Flop Inputs

22 Figure Three-bit Gray code counter. Step 6: Counter Implementation

23 Figure 9—32 : Example 9-5

24

25

26 Figure 9--33

27 Figure 9--34

28 Figure Example State diagram for a 3-bit up/down Gray code counter.

29

30

31 Figure J and K maps for Table The UP/DOWN control input, Y, is treated as a fourth variable.

32 Figure Three-bit up/down Gray code counter.

33 Figure Functional block diagram for parking garage control. Counter Applications : Automobile Parking Control

34 Figure Logic diagram for modulus-100 up/down counter for automobile parking control.

35 Figure Parallel-to-serial data conversion logic. Counter Applications : Parallel-to-Serial Data Conversion (Multiplexing)

36 Figure Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.

37 Figure Traffic light control system block diagram and light sequence. Application

38 Figure Block diagram of the sequential logic.

39 Figure State diagram showing the 2-bit Gray code sequence.

40 Figure Sequential logic.

41

42

43

44 Figure 9--70

45 Figure 9--71

46 Figure 9--72

You have invented a new type of flip-flop that you have called MY flip-flop. The two inputs are M and Y, the outputs are Q and Q'. The truth table of your flip-flop is given below. Show how to implement a SR flip-flop using the new MY flip-flop

Multiplexer Given the following implementation using a 4:1 multiplexer, what is the function L(A,B,C,D)? A.  m(0, 1, 2, 3) B.  m(5, 6, 8, 11) C.  m(1, 2, 5, 6) D.  m(1, 2, 5, 6, 9, 10, 13, 14) E.  m(2, 5, 9, 14) C D

Decoder