1. CHAPTER 3 Counters

2.  One of the common requirement in digital circuits/system is counting, both direction (forward and backward)  Digital clocks and watches are everywhere, timers are found in a range of appliances from microwave ovens to VCRs, and counters for other reasons are found in everything from automobiles to test equipment.  Although we will see many variations on the basic counter, they are all fundamentally very similar. INTRODUCTION

3.  Counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of classifications exist:  Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops  Synchronous counter – all state bits change under control of a single clock  Decade counter – counts through ten states per stage  Up/down counter – counts both up and down, under command of a control input  Ring counter – formed by a shift register with feedback connection in a ring  Johnson counter – a twisted ring counter  Cascaded counter  Each is useful for different applications INTRODUCTION (cont.)

4.  A counter – a group of flip-flops connected together to perform counting operations.  The number of flip-flops used and the way in which they are connected determine the number of states (modulus).  Two broad categories according to the way they are clocked:  Asynchronous counter  Synchronous counter

5. ASYNCHRONOUS COUNTER A 2-bit asynchronous binary counter.  Don’t have fixed time relationship with each other.  Triggering don’t occur at the same time.  Don’t have a common clock pulse

6. The Timing diagram Notice that :  Main clock pulse only applied to FF0.  Clock for next FF, taken from previous complemented output ( Q ).  All inputs (J, K) are high (Vcc).

7. The Timing diagram

8. The Binary State Sequence CLOCK PULSEQ1Q1 Q0Q0 Initially00 101 210 311 4 (recycles)00 0 1 1 0 1 1 0 00 0

9. Three-bit asynchronous binary counter and its timing diagram for one cycle.

10. The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSEQ2Q2 Q1Q1 Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles)000

11. Four-bit asynchronous binary counter and its timing diagram.

12. ASYNCHRONOUS DECADE COUNTER  The modulus of a counter is the number of unique states that the counter will sequence through.  The maximum possible number of states (max modulus) is 2 n where n is the number of flip-flops.  Counter with ten states are called decade counter.  Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2 n. The resulting sequence is called truncated sequence.  To obtain a truncated sequence it is necessary to force the counter to recycle before going through all of its possible states.

13. An asynchronously clocked decade counter

14. SYNCHRONOUS COUNTER OPERATION A 2-bit synchronous binary counter.

15. The Binary State Sequence CLOCK PULSEQ1Q1 Q0Q0 Initially00 101 210 311 4 (recycles)00 0 0 0 1 1 0 1 1 0 0

16. A 3-bit synchronous binary counter. 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

17. The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSEQ2Q2 Q1Q1 Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles)000

18. A 4-Bit Synchronous BCD Decade Counter.

19. The Binary State Sequence for BCD Decade Counter CLOCK PULSEQ3Q3 Q2Q2 Q1Q1 Q0Q0 Initially0000 10001 20010 30011 40100 50101 60110 70111 81000 91001 10 (recycles)0000

20. General clocked sequential circuit : DESIGN OF SYNCHRONOUS COUNTERS

21. Steps used in the design of sequential circuit: 1.Specify the counter sequence and draw a state diagram 2.Derive a next-state table from the state diagram Develop a transition table showing the flip-flop inputs required for each transition. *** Transition/Excitation Table will be given. 3.Transfer the J and K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input. 4.Implement the expressions with combinational logic, and combine with the flip-flops to create the counter (construct the counter).

22. Example: Design a counter for 3-bit Gray code by using J-K Flip-flop. 0 1 3 2 6 7 5 4 0 1.…….. 1.State Diagram

23. 2. Next-state table for a 3-bit Gray code counter. Present State Next State Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q0 000001 001011 011010 010110 110111 111101 101100 100000

24. Transition Table for a J-K flip-flop Output TransitionsFlip-flop Inputs QNQN Q N+1 JK 0  00X 0  11X 1  0X1 1  1X0 Q N : present state Q N+1: next state X: Don’t care

25. 3. Karnaugh maps for present-state J and K inputs.

26. 4. Three-bit Gray code counter

27. Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-flops. 1. State Diagram

28. 2. Next-state table Present State Next State Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q0 001010 010101 101111 111001

29. Transition Table for a J-K flip-flop Output TransitionsFlip-flop Inputs QNQN Q N+1 JK 0  00X 0  11X 1  0X1 1  1X0

30. 3. K-Map

31. 4. The Counter Circuit

32. Transition/Excitation Table for Flip-flop

33. Example: State diagram for a 3-bit up/down Gray code counter.

34. UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

35. Timing Diagram

36. The 74HC190 up/down synchronous decade counter.

37. Timing example for a 74HC190.

38. J and K maps - The UP/DOWN control input, Y, is treated as a fourth variable.

39. Three-bit up/down Gray code counter

40. CASCADE COUNTERS Two cascaded counters (all J and K inputs are HIGH).

41. A modulus-100 counter using two cascaded decade counters.

42. Three cascaded decade counters forming a divide-by- 1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

43. Example: Determine the overall modulus of the two cascaded counter for (a) and (b) For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

44. A divide-by-100 counter using two 74LS160 decade counters.

45. A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D 0 is the LSB in each counter).

46. Decoding of state 6 (110). COUNTER DECODING * To determine when the counter is in a certain states in its sequence by using decoders or logic gates.

47. A 3-bit counter with active-HIGH decoding of count 2 and count 7.

48. A basic decade (BCD) counter and decoder.

49. Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

50. The basic decade counter and decoder with strobing to eliminate glitches.

51. Strobed decoder outputs for the circuit

52. Simplified logic diagram for a 12-hour digital clock.

53. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

54. Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

55. Functional block diagram for parking garage control.

56. Logic diagram for modulus-100 up/down counter for automobile parking control.

57. Parallel-to-serial data conversion logic.

58. Example of parallel-to-serial conversion timing for the previous circuit