1. Chapter 1 Counters

2. Counters Counters are sequential circuits which "count” through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: 1. Ripple counters (Asynchronous counter) 2. Synchronous counter

3. Ripple Counters – Clock is connected to the flip-flop clock input on the LSB bit flip-flop – For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous – Output change is delayed more for each bit toward the MSB. – Resurgent because of low power consumption

4. Revision of Ripple Counters Let’s look at some slides from Digit 1. Let’s look at some slides from Digit 1.

5. A 2-bit asynchronous (ripple) binary counter (Rev) Both flip-flops are assumed to be initially RESET (Q low) Both flip-flops are assumed to be initially RESET (Q low) Q 0 is always the LSB unless otherwise specified Q 0 is always the LSB unless otherwise specified

6. The Timing diagram for 2 bit Asynchronous Binary Counter (Rev) This is a complete timing diagram & propagation delay time are not indicated. This is a complete timing diagram & propagation delay time are not indicated. Delay timing are normally omitted for simplicity but it is very important in design & troubleshooting purposes Delay timing are normally omitted for simplicity but it is very important in design & troubleshooting purposes

7. The Binary State Sequence for 2 bit Asynchronous Binary Counter (Rev) CLOCK PULSE Q1Q0 Initially00 101 210 311 4 (recycles) 00

8. Ripple Counter How does it works? How does it works? – When there is a positive Clock edge on the clock input of A, A complements – The clock input for flip flop B is the Complemented output of flip-flop A – When flip A changes from 1 to 0, there is a positive edge on the clock input of B causing B to complement

9. 3-bit asynchronous binary counter and its timing diagram for one cycle. (Rev)

10. The Binary State Sequence for a 3- bit Binary Counter (Rev) CLOCK PULSE Q2Q2Q2Q2 Q1Q1Q1Q1 Q0Q0Q0Q0 Initially000 1001 2010 3011 4100 5101 6110 7111 8 (recycles) 000

11. Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter (Rev)

12. Ripple Counter

13. Four-bit asynchronous binary counter and its timing diagram (Rev)

14. Ripple Counter The arrows show the cause-effect relationship The corresponding sequence of states => (B,A) = (0,0),(0,1), (1,0), (1,1), (0,0), (0,1), … Each additional bit, C, D, …behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …

15. Ripple Counter These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop’s state. The changes “ripple” upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. To see this effect in detail look at the waveforms on the next slide.

16. Ripple Counter

17. Starting with C = B = A = 1, equivalent to (C,B,A) = 7 base 10, the next clock increments the count to (C,B,A) = 0 base 10. In fine timing detail: – The clock to output delay tPHL causes an increasing delay from clock edge for A each stage transition. – Thus, the count “ripples” from least to most B significant bit. – For n bits, total worst case C delay is n tPHL.

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19. Synchronous Counters – Clock is directly connected to the flip-flop clock inputs – Logic is used to implement the desired state sequencing

20. Revision of synchronous counter Slides from Digit 1 Slides from Digit 1

21. SYNCHRONOUS COUNTERS (Rev) All the flip-flops in the counter are clocked at the same time by a common clock pulse (external clock) All the flip-flops in the counter are clocked at the same time by a common clock pulse (external clock) 2 advantages compared to Asynchronous Counter : 2 advantages compared to Asynchronous Counter : 1) Very less propagation delay time 1) Very less propagation delay time 2) Able to perform counting in random mode 2) Able to perform counting in random mode (eg : 0,1,3,5,8, …,0,1,3,5,8,..) (eg : 0,1,3,5,8, …,0,1,3,5,8,..)

22. A 2-bit synchronous binary counter (Rev) Assumed initial in binary 0 states meaning that both flip--flops are in RESET condition. Assumed initial in binary 0 states meaning that both flip--flops are in RESET condition.

23. Timing diagram for 2-bit synchronous counter (Rev)

24. A 3-bit synchronous binary counter (Rev)

25. JKFF Truth Table JKQt 00 N. Change 010 101 11Toggle

26. JKFF Transition Table QtQt+1JK 000x 011x 10x1 11x0

27. Timing diagram for the counter (Rev)

28. Revision of Up / Down Counter

29. A basic 3-bit up/down synchronous counter (Rev)

30. Up/Down Synchronous Counter (Rev) Up Synchronous Counter : Up Synchronous Counter : UP is set to ‘1’ and AND gate 1 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 2 also active causes Q2 toggling UP is set to ‘1’ and AND gate 1 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 2 also active causes Q2 toggling Because of JK connection from Q output, the counting sequence is UP. Because of JK connection from Q output, the counting sequence is UP. Down Synchronous Counter : Down Synchronous Counter : DOWN is set to ‘1’ and AND gate 3 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 4 also active causes Q2 toggling DOWN is set to ‘1’ and AND gate 3 is active causing output OR gate 1 is HIGH. This will cause Q1 output toggling. The AND gate 4 also active causes Q2 toggling Because of JK connection from Q output, the counting sequence is UP Because of JK connection from Q output, the counting sequence is UP

31. Timing Diagram Up/Down Synchronous Counter (Rev)

32. Other Counters – Down Counter - counts downward instead of upward – Up-Down Counter - counts up or down depending on value a control input such as Up/Down – Parallel Load Counter - Has parallel load of values available depending on control input such as Load Divide-by-n (Modulo n) Counter – Count is remainder of division by n which n may not be a power of 2 or – Count is arbitrary sequence of n states specifically designed state-by-state – Includes modulo 10 which is the BCD counter

33. Thank You.