© 2010 Altera Corporation—Public DSP Innovations in 28-nm FPGAs Danny Biran Senior VP of Marketing

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Ever-Increasing Bandwidth… 2 ….Demands ever-increasing processing performance

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. High bandwidth I/O  High-speed transceivers up to 28-Gbps (total 1.6 Tbps)  Up to 7 x 72-bit 1,600 Mbps DDR3 interfaces High performance core  More than 1M logic elements  More than 50 Mb of RAM  High-performance, variable-precision DSP with up to 3, x 18 multipliers (1,840 GMACS)  Application-targeted hard IP Power and cost  3 rd Generation Programmable Power Technology  HardCopy V ASIC provides risk-free path to ASIC New capabilities  Embedded HardCopy Blocks  Partial reconfiguration Stratix V FPGAs – “More Than Moore”

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Increasing Processing with Strict Power and Cost Budgets 44 Processing Price/Power Time

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Video Processing 5 Standard Definition 0.4M pixels per frame 9 x 9 precision High Definition (1080p) 2M pixels per frame 9 x 9 → 12 x 12 precision 4K Resolution ~10M pixels per frame 9 x 9 → 18 x 18 precision DSP performance  25X pixels processed per frame

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Wireless Evolution 6 Single antenna 5 MHz, 1 carrier 18 x 18 precision 10 Mbps100 Mbps1,000 Mbps 2 x 2 MIMO 20 MHz, 1 carrier 18 x 18 precision 4x4 MIMO MHz, 5 carrier 18 x 18 → 27 x 27 precision 3G LTE LTE Advanced DSP performance  200X (multiple carriers, multiple antennae)

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Military Radar 7 Ground mapping and see-thru wall radars Limited Target Detection  Simultaneous multiple target detection  1000s of transmit- receive modules  100s of sub-channels DSP performance → 100X (multiple targets and transmit-receive modules) Up to Floating-Point Precision 18x18 precision

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Today’s FPGA DSP Technology Does NOT Scale 8 Video Surveillance Broadcast Systems Wireless Basestations Medical Imaging Military Radar High-Performance Computing 100 GMAC/s 9-bit Precision TERA FLOPs Floating-Point Precision Fixed-precision DSP architecture can not meet increasing performance needs within cost and power budgets

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. 9 Set the precision dial to match your application Industry’s First Variable-Precision DSP Block

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. New Levels of DSP FPGA Performance 10 1,840 GMACS or 1,000 GFLOPS performance in a single device FPGA Industry Firsts Integrated coefficient registers 64-bit cascade and adder to implement higher precision data-paths Efficient support for floating-point DSP High-Precision Mode 18-bit Precision Mode

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Variable-Precision DSP Advantage Price and Power 11 Video Processing Wireless Basestations Military Radar Fixed Precision ⅓ DSP Resources ½ DSP Resources ½ DSP Resources Variable Precision Fixed Precision Variable Precision Variable Precision Fixed Precision

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Total DSP Portfolio 12 DSP Block Architecture Total DSP Solutions Video Design Framework DSP Builder Timing-Driven Simulink Synthesis Comprehensive Floating-Point IP

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Altera Video Design Framework 13 Higher designer productivity = Faster time to market

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Altera Video Design Framework Customer Application 14 Video Wall Over 100 active customers to date Altera Video Framework Function Image: Apantac LLC. Color Space Conversion CRS and Color Space Conversion CRS and Color Space Conversion Motion-Adaptive Deinterlacing Clipping Proprietary Video Processing Clipping Scaling Color Space Conversion + CRS Color Space Conversion + CRS Test Pattern Generation Motion-Adaptive Deinterlacing Video Mixer Composite Image Clipping Video 1 Video 2 Video 3 Video 4

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. DSP Builder Advanced Blockset (DSPB-AB) 15 HDL automatically optimized for system clock frequency and latency

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Altera’s Floating-Point Portfolio 16 FFT MegaCore offers floating-point option Sine and cosine: Expected in Quartus software v.10.1 Largest portfolio of floating-point cores

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Replacing Floating-Point Digital Signal Processors in Radar Systems Stratix V FPGA (EP5SGSB7 ) DSP Farm* Performance~700 GFLOPS~90 GFLOPS Power~60 W~128 W 17 * 32 floating-point digital signal processors—2.7 GFLOP/s, 4 W each Industry’s highest floating-point processing at the lowest power

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Replacing Multicore Digital Signal Processors in a LTE Channel Card 18 Stratix V FPGA (EP5SGXA3) Multicore Digital Signal Processors Performance~200 GMAC/s~50 GMAC/s Power~10 to 20 W

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Choice of LTE Towards a FPGA-Centric Architecture 19 DSP Centric FPGA Centric

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Replacing ASSPs and Digital Signal Processors in High-End Conferencing Systems Video Design Framework Performance System Costs

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Summary Expanding bandwidth demands driving need for increased processing performance Fixed-precision DSP blocks cannot meet increasing performance needs within cost and power budgets Altera is offering industry’s first variable-precision DSP block Altera’s DSP solution is replacing digital signal processors and ASSPs 21