Bulk MEMS 2013, Part 2 sami.franssila@aalto.fi

Micro hot plate: how many litho steps ? 0. Double side polished <100> wafer LPCVD nitride Litho on backside for nitride Nitride RIE & resist strip Pt sputter Litho of Pt heater Pt etch & strip CVD oxide Litho to reveal Pt heater for wire bond Oxide etch & strip Litho of Pt measurement electrodes Pt etch & resist strip Frontside protection (jig) Backside KOH etch Sensor material depo & patterning Pt heater Nitride Pt measurement electrodes sensor material oxide

<Si> microbridges Backside micromachining Need front-to-back alignment Bridge thickness free variable May use p++ etch stop May use KOH and/or DRIE Front side micromachining Alignment on front only Needs p++ etch stop Depends on p++ selectivity Needs epi for thick bridge Wider bridge  depth under larger

Double side alignment Double sided lithography requires DSP wafers (Double Side Polished) Some alignments are critical but not all ! Often the backside structures are large, and not critically aligned to top side features.

Alignment: diffused piezoresistors OK NOT OK Piezoresistors have to be positioned at the maximum defelection region

Silicon microbridges Material Bridge definition Bridge release Figure   bulk <100> front side DRIE backside wet 30.1 p++ <100> front side p++ doping front side KOH 30.1 <111> front side DRIE twice front side KOH 20.34 bulk <100> front side DRIE front isotropic plasma 21.13 bulk <100> front side doping porous silicon etching 23.27 SOI front side DRIE handle wafer isotropic 21.14 SOI front side DRIE BOX etching 29.1 SOI front side DRIE notching effect 21.28 cavity SOI front side DRIE none required 30.18

Bonded SOI (Silicon On Insulator) Thermally oxidized wafer is joined to another silicon wafer. After bond improvement anneal and thinning, the resulting 3-layer structure can be processed as any silicon wafer. Oxide layer thickness 100 nm – 1 µm (4 µm available as an expensive option) Top silicon thickness anything, but 5-50 µm typical in MEMS RCA-1 clean RT joining HT anneal thinning edge conditioning

SOI microbridge DRIE of device <Si> with oxide mask Buried oxide etch stop CVD oxide deposition to protect sides Buried oxide RIE (=anisotropic) (mask oxide thicker than buried oxide) Isotropic <Si> etch in SF6

Ink jet

Ink jet (2) Process flow for ink jet: Thermal oxidation, 1 µm thick   Thermal oxidation, 1 µm thick Litho #1: chip area definition Oxide etching Boron diffusion, 2 µm deep Litho #2: chevron pattern: 1 µm width RIE of silicon, 4 µm deep Anisotropic silicon etching to undercut p++ chevrons Thermal oxidation LPCVD nitride deposition for chevron roof sealing Etchback (or polishing) of nitride LPCVD polysilicon deposition Poly doping, 20 Ohm/sq

Ink jet (4) Litho #3: poly heater pattern Polysilicon etching Aluminum sputtering Litho #4: metal pads Aluminum etching Passivation: CVD oxide 1 µm + PECVD nitride 0.3 µm Lithography #5: opening of bonding pads RIE of nitride and oxide Lithography #6: pattern for gold lift-off Evaporation of Cr/Au Lift of Cr/Au Lithography #7: fluidic inlet definition on the backside Anisotropic etching through the wafer from the back   Resist stripping and cleaning steps omitted

AFM tips: thru-wafer SOI wafer with 5-μm thick device layer thermal oxidation LPCVD nitride etch nitride from front side (no litho) lithography for the tip etch oxide etch silicon pyramid and remove mask oxide thermal oxidation for tip-sharpening lithography to define the cantilever DRIE of device silicon (+resist strip) thermal oxidation for passivation lithography for piezoresistors boron implantation for resistors (+strip) lithography & etch for contact boron implantation for contacts (+ strip) implant activation in RTA aluminum deposition, litho, etch, strip Front protection: polyimide spinning backside nitride litho & etch & strip backside TMAH anisotropic etch buried oxide etching polyimide plasma removal

In-plane vs. out-of-plane needles

Mirrors: in-plane and out-of-plane

Out-of-plane mirror on SOI (1)

Out-of-plane mirror on SOI (2)

Bonding: critical vs. non-critical Microchannel defined by bonding Capacitor gap defined by bonding

Bonded microphone Membrane (top) wafer: Thermal oxidation & oxide patterning Nitride deposition & top side nitride etch Membrane metallization (Cr/Au) KOH etch half way Silicon backplate wafer: Oxidation Peeling mask KOH etching Metallization (Cr/Au) Final processing: Gold-gold thermocompression bonding Aluminum metallization through shadow mask Fig. 30.8

Another bonded microphone Backplate chip with acoustic holes Membrane chip with Au/Sn solder bumbs acoustic holes air gap

IR spectrometer

Integrated accelerometer Anodic bonding: silicon-to-glass Hermetic cavity (vacuum) Takao, H. et al: A CMOS integrated three-axis accelerometer fabricated with commercial CMOS technology and bulk micromachining, IEEE TED 48 (2001), p. 1961

Packaging by capping wafer

Packaging by capping wafer (2)

Cavity-SOI oxide Al electrode Si membrane ground electrode air cavity

Cavity-SOI fabrication oxide Al electrode Si membrane ground electrode air cavity silicon Lithography of air cavity DRIE of silicon & strip PR Cleaning Thermal oxidation Bonding with a bulk wafer Thinning by KOH Al sputtering Litho & Al etch & strip CVD oxide

C-SOI: No need for release etching

CMOS-MEMS integration

CMOS-MEMS (2) Dougherty, JMEMS 2003 a b c d Dougherty, JMEMS 2003 DRIE and semipermeable polysilicon deposition; buried oxide etching through semi-permeable poly deposition of standard polysilicon and CMP IC processing and release hole etching by DRIE

CMOS-MEMS a) thin film MEMS by front side dry plasma release; b) single crystal silicon MEMS by backside DRIE

Bulk vs. SOI Wet etching Electrochemical etch stop Large useless area d Wet etching Electrochemical etch stop Large useless area DRIE etching Easy etch stop by BOX MEMS and CMOS side by side not area efficient

Summary Wafer selection: <100> SSP wafers ? <100> DSP wafers ? SOI wafers ? Materials compatibility: How high temperature does glass wafer tolerate ? Can cavity-SOI really be processed like standard wafer ? What are the limitations of piezoelectric materials ? Process-device interactions: Can thermal diffusion be used or is I/I preferred ? Is DRIE etch profile ciritical or non-critical Will the wafers bend due to thin film stresses ? Equipment and process capability: How can we clean wafers with released structures ? How thick roof can we deposit ? Can thick bonded wafer stacks be inserted to wafer boats ?

Summary (2) Design rules: What is the smallest allowed linewidth on front side ? What is the minimum linewidth for backside thru-wafer DRIE ? What is front-to-back alignment accuracy ? Mask considerations: Which photomasks are critical, which are non-critical ? Does etch undercutting need to be compensated on the mask ? Order of process steps: Should front side processing be completed before backside processing ? Can any steps be done after thin membrane formation ? Can any steps be done after thru-wafer holes have been made ? Reliability: How do stresses build up when more layers are deposited ? What vacuum does the resonator cavity need ? What leak rate is allowed in the resonator cavity ?