Sundance High-tech DSP solutions. Giving you the freedom to design Multiprocessor Technology Ltd SYSTEM CONFIGURATION

CARRIER BOARD PCI HOST/Carrier Board PCI HOST Host Comport Global bus TIM1TIM2TIM3TIM4 Master Config line Reset

DSP module TIMn FLASHFLASH DSP FPGA bitstreams bootloader User data application FPGA Init Power-up Reset Run Communication resources Config. load bootloader bitstreams User data application

FPGA module with PROM Power-up Reset TIMn PROMPROM CPLD FPGA FPGA Init Config. load bitstream Xilinx Parallel Cable IV JTAG Communication resources Run

FPGA module via comport Power-up Reset TIMn CPLD FPGA FPGA Init Communication resources Config. load ComPort Transmitter bitstream ComPort Run

TIM1 FLASHFLASH DSP FPGA System with Host TIM2 CPLD or MSP430 FPGA HOST bitstream Links ComPort Reset Communication resources TIM connector

Reconfiguring with the Config line TIM1 FLASHFLASH DSP FPGA TIM2 CPLD or MSP430 FPGA HOST bitstream Reset Communication resources Config Links ComPort TIM connector

Slave SelectMap mode FPGA configuration Power-up Reset - The PROGRAM and INIT pins are both driven Low by the FPGA. Run Configuration sequence - The global reset signals are toggled when the DONE pin goes High. FPGA Init - PROGRAM goes High and INIT goes High a short time later. The device can remain permanently in this state if either PROGRAM or INIT are held Low. Config. load - After INIT has gone High, the mode pins [M2..M0] are sampled on the rising edge of CCLK.