1. Monitor ROM Module MTT48 V2.1 17 - 1 MONITOR ROM MODULE (MON)

3. Monitor ROM Module MTT48 V2.1 17 - 3 Module Objective Understand how to use the Monitor ROM, which alllows complete testing of the MCU through a single-wire interface with a host computer.

4. Monitor ROM Module MTT48 V2.1 17 - 4 MONITOR MODULE 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable Memory (EPROM) LVI COP Monitor ROM IRQ BREAK RESET Normal User-Mode Pin Functionality One Pin Dedicated to Serial Communication between Monitor ROM and Host Computer Standard Mark/Space Non-Return-to-Zero (NRZ) Communication with Host Computer 4800 Baud–28.8 kBaud Communication with Host Computer Execution of Code in RAM or ROM (E)EPROM/OTPROM Programming

5. Monitor ROM Module MTT48 V2.1 17 - 5 Monitor Mode (MON) Operation Receives and executes commands from a host computer –Communicates via a standard RS-232 interface –Communication is standard non-return-to-zero (NRZ) All communication between Host and MCU is through the PTA0 pin –A level-shifting and multiplexing interface is required between PTA0 and Host. –PTA0 used in a wired- OR configuration and requires a pulll-up resistor To indicate MCU is ready to receive command –MCU sends break signal(10 consecutive logic zeros) to host computer –Break signal also provides timing reference for host to determine necessary baud rate(must be identical). °baud rate range: 4800 baud to 28.8 Kbaud Monitor ROM immediately echoes each received byte back to the PTA0 pin for error checking

6. Monitor ROM Module MTT48 V2.1 17 - 6 Monitor Mode Selection Three external pins examined at rising edge of RST Conditions for entering Monitor operating mode Enter Monitor mode by either –Executing a software interrupt instruction(SWI) or –Applying a logic zero and then a logic one to the RST pin Reset vector fetched from $FEFE - $FEFF rather than $FFFE - $FFFF Executes program in monitor ROM, $FE10 - $FEFF IRQ1/Vpp PIN PTC0 PIN PTC1 PIN PTA0 PIN PTC3 PIN Mode CGMOUT Bus Frequency 11 01 1 0 10 Monitor V DD + V HI CGMOUT/2 CGMXCLK/2 or CGMVCLK/2 CGMXCLK

7. Monitor ROM Module MTT48 V2.1 17 - 7 Sample Circuit to enter Monitor Mode

8. Monitor ROM Module MTT48 V2.1 17 - 8 Mode Differences COP MODES FUNCTIONS MONITOR USER BREAK VECTOR LOW BREAK VECTOR HIGH RESET VECTOR LOW RESET VECTOR HIGH SWI VECTOR LOW SWI VECTOR HIGH $FFFE $FEFF ENABLED $FEFC$FEFD $FFFD $FFFC $FFFD $FFFC $FEFE $FFFF DISABLED $FEFC

9. Monitor ROM Module MTT48 V2.1 17 - 9 Monitor ROM Commands READ Read memory WRITE Write memory IREAD Indexed Read IWRITE Indexed Write READSP Read Stack Pointer RUN Run User Program Command Description

10. Monitor ROM Module MTT48 V2.1 17 - 10 Operand Specifies 2-bute address in high byte:low byte order Returns contents of specified address $4A Data Returned Opcode Command Sequence Description Read Byte from Memory Operand Specifies 2-bute address in high byte:low byte order; low byte followed by data byte None $49 Data Returned Opcode Command Sequence Description Write Byte from Memory READ(Read memory) Command WRITE(Write memory) Command

11. Monitor ROM Module MTT48 V2.1 17 - 11 Operand Specifies 2-bute address in high byte:low byte order Returns contents of next two address $1A Data Returned Opcode Command Sequence Description Read next 2 bytes in memory from last address access Operand Specifies single data byte None $19 Data Returned Opcode Command Sequence Description Write to last address accessed + 1 IREAD(Indexed Read) Command IWRITE(Indexed Write) Command

12. Monitor ROM Module MTT48 V2.1 17 - 12 Operand None Returns stack pointer in high byte:low byte order $OC Data Returned Opcode Command Sequence Description Reads Stack Pointer Operand None $28 Data Returned Opcode Command Sequence Description Executes RTI intstruction READSP(Read Stack Pointer) Command RUN(Run User Program) Command