An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets Abhijit Jas, Kartik Mohanram, and Nur A. Touba Eighth Asian Test Symposium, (ATS '99), Page(s): Presented by Kao, Chung-Fu

What’s the Problem ? How to reduce the core testing time ? How to use a very small number of test vectors ? If it’s necessary to modify a core, does it compatible with ordinary core ?

Introduction The difficulty and cost of testing SOC are escalating rapidly. The idea is to create a DFHTC (Design for High Test Compression) core – Can be tested with a small number of test vectors compared to the ordinary core

Introduction (cont’d) Internally, the actual number of test vectors that are applied to the core is much larger. – Compress test vectors outside This methodology uses PRPG (Pseudo Random Pattern Generators) mechanism.

It’s different from BIST The disadvantages of BIST – Non-trivial to achieve high fault coverage – Should insert some test points – Pure BIST required long test lengths The advantages of DFHTC core – Compatible with scan chain design – Achieves a high fault coverage

Architecture Overview Serial In Parallel Out Shift register

Action 1. Initial Seed 2. Serial input 3. Scan finish 4. Parallel input to all PRPGs and locks the First PRPG

Example of Test Vectors The highlighted (red) portions of the test vectors have been shifted into the core from outside, and the PRPG has been locked. T T T T

Constructing a Highly Compressed Scan Vector Assume that we have a CUT with bN inputs – N PRPGs each b bits wide ATPG – target some undetected fault

Experimental Results

Conclusion A DFHTC core reduces test time and tester memory requirements. The DFHTC mechanism is compatible with ordinary cores – Has the same test I/O pins, can use the same tester program A DFHTC core will reduce test costs for system integrator.