1. A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume Wei-Cheng Lien 1, Kuen-Jong Lee 1 and Tong-Yu Hsieh 2 1 Dept. of Electrical Engineering, National Cheng Kung Univ., Taiwan 2 Dept. of Electrical Engineering, National Sun Yat-sen Univ., Taiwan

2. 2 Asia Test Symposium 2012 Outline Introduction Previous Work Proposed Concurrent Multiple Test Embedding Procedure Experimental Results Comparisons Conclusions

3. 3 Asia Test Symposium 2012 Employ some specific on-chip test structure to test a circuit itself.  Pseudo Random Testing  Mixed-mode BIST Reseeding Mapping Logic  Deterministic BIST Twisted Ring Counter (TRC) LFSRLFSR Mapping Logic ROM Introduction – Logic Built-In Self-Test (BIST) Circuit Under Test In this paper we will focus on test-per-clock LFSR reseeding algorithm to reduce test sequence length and test data volume.

4. 4 Asia Test Symposium 2012 Previous Reseeding Algorithms Previous test-per-clock reseeding methods mainly comprise 3 steps.  Step 1: Seed Selection Select one pattern as an initial seed from a given test set.  Step 2: Test Sequence Generation Generate a fixed length of test sequence.  Step 3: Test Set Embedding Select pattern one-by-one. Embed as many patterns as possible. (Pattern-Oriented) Go back to Step 1 if no patterns in the remaining test set can be embedded. Pseudo Random Pattern 1 … Pseudo Random Pattern 2 Pseudo Random Pattern 3 Step 2 Pattern 3 A pre-defined partially- specified test set Pattern 1 Pattern 2 Pattern 3 … Pattern 2 (Seed) Step 1 Pseudo Random Pattern N Step 3

5. 5 Asia Test Symposium 2012 Features of Proposed Reseeding Algorithm Compared with previous reseeding algorithms, our reseeding technique (called concurrent multiple test embedding method) has the following distinguishing features to determine one seed.  Step 1: Test Sequence Generation Start with a fully-unspecified pattern as an initial seed. Incrementally increase the test sequence length only when necessary.  Step 2: Candidate Pattern Generation Directly fill the X-bits of the newly-added test sequence to generate candidate patterns for test embedding.  Step 3: Test Set Embedding Embed multiple candidate patterns at one time. Detect as many undetected faults as possible (Fault- Oriented)

6. 6 Asia Test Symposium 2012 Concurrent Multiple Test Embedding Procedure Apply random patterns to extract hard-to-detect faults from F T and store them to F HD A testable faults list F T Perform seed determination process to generate one seed S i for F HD and drop all detected faults from F HD i ← 1 i ← i + 1 Is F HD empty? Perform seed reusing process to reuse all generated seeds in S to drop all detected faults from F T Is F T empty? i ← i + 1 No Yes No Add S i to S Perform seed determination process to generate one seed S i for F T and drop all detected faults from F T Add S i to S END Yes Test Sequence Generation Candidate Pattern Generation Test Set Embedding seed determination process

7. 7 Asia Test Symposium 2012 Assume the CUT has 5 inputs from I 1 to I 5, 15 faults from f 1 to f 15 and P(x) = 1 + x 2 + x 5. Use an user-defined input parameter LCS to limit the maximum number of consecutive redundant patterns during test sequence generation. (LCS = 6 in our example) Seed Determination – Test Sequence Generation x x x x x LS 2 x 2 ⊕ x 5 x 1 x 2 x 3 x 4 x x x x x LS 3 x 1 ⊕ x 4 x 2 ⊕ x 5 x 1 x 2 x 3 x x x x x LS 4 x 2 ⊕ x 3 ⊕ x 5 x 1 ⊕ x 4 x 2 ⊕ x 5 x 1 x 2 x x x x x LS 5 x 1 ⊕ x 2 ⊕ x 4 x 2 ⊕ x 3 ⊕ x 5 x 1 ⊕ x 4 x 2 ⊕ x 5 x 1 x x x x x LS 6 x 1 ⊕ x 2 ⊕ x 3 ⊕ x 5 x 1 ⊕ x 2 ⊕ x 4 x 2 ⊕ x 3 ⊕ x 5 x 1 ⊕ x 4 x 2 ⊕ x 5 x x x x x x 1 x 2 x 3 x 4 x 5 LS 1 I 1 I 2 I 3 I 4 I 5 Pseudo Random Pattern Equation

8. 8 Asia Test Symposium 2012 Specify the X-bits in the newly-added pseudo random patterns to generate candidate patterns for test embedding. Seed Determination – Candidate Pattern Generation x x x x x LS 2 x x x x x LS 3 x x x x x LS 4 x x x x x LS 5 x x x x x LS 6 x 0 1 x 1 x 1 0 0 0 P2P2 P1P1 x 1 1 0 1 P3P3 0 x 0 x 1 P4P4 1 1 1 1 x P5P5 1 x 0 x 1 P6P6 LS 1 f 2 f 6 f 7 f 15 f 5 f 9 f 10 f 12 f 1 f 3 f 14 f 4 f 11 f8f8 f 13 Detect Faults X-filling 6 pattern pairs (P 1, LS 1 ) (P 2, LS 2 ) (P 3, LS 3 ) (P 4, LS 4 ) (P 5, LS 5 ) (P 6, LS 6 ) Candidate Patterns

9. 9 Asia Test Symposium 2012 x x x x x LS 2 x x x x x LS 3 x x x x x LS 4 x x x x x LS 5 x x x x x LS 6 x 0 1 x 1 x 1 0 0 0 P2P2 P1P1 x 1 1 0 1 P3P3 0 x 0 x 1 P4P4 1 1 1 1 x P5P5 1 x 0 x 1 P6P6 x 2 = 0 x 3 = 1 x 5 = 1 x 1 = 1 x 2 = 0 x 3 = 0 x 4 = 0 x 1 = 1 x 2 = 0 x 3 = 1 x 5 = 1 x 2 = 1 x 3 = 0 x 5 = 1 x 2 = 0 x 3 = 0 x 5 = 1 x 1 ⊕ x 4 = 1 x 1 = 1 x 3 = 1 x 2 ⊕ x 5 = 1 LS 1 Seed Solution of Each Pattern Pair Compatibility Graph 6 candidate pattern pairs P 1, LS 1 P 3, LS 3 P 6, LS 6 P 4, LS 4 P 5, LS 5 P 2, LS 2 Seed Determination – Test Set Embedding (1/3) 6 candidate pattern pairs (P 1, LS 1 ) (P 2, LS 2 ) (P 3, LS 3 ) (P 4, LS 4 ) (P 5, LS 5 ) (P 6, LS 6 )

10. 10 Asia Test Symposium 2012 P2P2 P1P1 P3P3 P4P4 P5P5 P6P6 f 2 f 6 f 7 f 15 f 5 f 9 f 10 f 12 f 1 f 3 f 14 f 4 f 11 f8f8 f 13 Detect Faults 4+(3+1)/2 = 6 4+(1)/1 = 5 3+(4+1)/2 = 5.5 2 1+(4)/1 = 5 1+(4+3)/2 = 4.5 Weight of (P i, LS j ) P 1, LS 1 P 3, LS 3 P 6, LS 6 P 4, LS 4 P 5, LS 5 P 2, LS 2 Compatibility Graph Weight = 6 Weight = 5.5Weight = 4.5Weight = 5 Weight = 2 Seed Determination – Test Set Embedding (2/3) Weight of (P 1, LS 1 ) = 4 (#faults detected by P 1 ) + {3 (#faults detected by P 3 ) + 1 (#faults detected by P 6 ) } /2 = 6

11. 11 Asia Test Symposium 2012 P 1, LS 1 P 3, LS 3 P 6, LS 6 Compatibility Graph Weight = 6 Weight = 5.5Weight = 4.5 P 4, LS 4 P 5, LS 5 P 2, LS 2 Weight = 5 Weight = 2 Embed multiple candidate patterns to detect most undetected faults at one time. P 1, LS 1 Weight = 4 (P 1, LS 1 ) (P 3, LS 3 ) (P 6, LS 6 ) x 2 = 0 x 3 = 1 x 5 = 1 x 1 = 1 x 2 = 0 x 3 = 1 x 5 = 1 x 1 = 1 x 3 = 1 x 2 ⊕ x 5 = 1 P 3, LS 3 Weight = 1 P 6, LS 6 x 1 = 1 x 2 = 0 x 3 = 1 x 5 = 1 Seed Solution Update All Patterns 1 0 1 x 1 1 1 0 1 x LS 2 LS 1 x 1 1 0 1 LS 3 0 x 1 1 0 LS 4 x 0 x 1 1 LS 5 1 x 0 x 1 LS 6 Seed Determination – Test Set Embedding (3/3)

12. 12 Asia Test Symposium 2012 1 0 1 x 1 1 1 0 1 x LS 2 LS 1 x 1 1 0 1 LS 3 0 x 1 1 0 LS 4 x 0 x 1 1 LS 5 1 x 0 x 1 LS 6 Seed Determination – Termination Conditions X-filling P1P1 0 x 0 x 1 Fault Coverage (FC) = 8/15 = 53% 7 Undetected Faults = { f 4 f 5 f 8 f 9 f 10 f 11 f 12 } 4 0 3 0 0 1 #detected faults 1 0 1 1 1 LS 1 4 1 1 0 1 1 LS 2 00 1 1 0 1 LS 3 30 0 1 1 0 LS 4 00 0 0 1 1 LS 5 21 0 0 0 1 LS 6 1 x 4 = 1 Seed Solution f 4 f 11 Detect Faults FC=10/15=67% 1 1 0 0 0 LS 7 f 5 f 9 f 10 f 12 4 FC=14/15=93% 1 1 1 0 0 LS 8 01 1 1 1 0 LS 9 1 f8f8 FC=15/15=100% Update All Patterns Termination Conditions: 1.All faults are detected. 2. LCS consecutive patterns can not detect any new faults even after applying test embedding. => Identify a new seed.

13. 13 Asia Test Symposium 2012 We reuse the generated seeds for F HD to detect all testable faults first and drop all faults detected by the generated seeds from F T. If some testable faults in F T are still undetected, we will further utilize the remaining X-bits in those seeds to detect more faults.  Sort all generated seeds in increasing order of their derived test sequence length.  Select the seed according to their sorting order.  Use the seed determination process again for the target seed to detect undetected faults in F T.  Terminate until all testable faults are detected. Otherwise, identify more seeds for all remaining faults after considering all current seeds. Seed Reusing Process

14. 14 Asia Test Symposium 2012 Circuit Name #IN|F T | |F HD |/|F T | % ATPG Test SetProposed LFSR Reseeding #TPS max |S| #TP (BIST) #Storage Bits RD % c499417505.875441439916492.59 c880609421.803157451124087.10 c13554115661.2884411290849285.71 c19083318703.961163316132752886.21 c2670233263012.09562006827139889.29 c35405032911.34131448137840093.89 c531517852930.3872162382653495.83 c755220774196.3698194141450289885.71 Our method can achieve 100% fault coverage with a small number of seeds (storage data volume) and very short test sequence length (test time). 100% stuck-at fault coverage is targeted and the input parameter LCS (limit on the number of consecutive redundant patterns) is set to 60. Experimental Results – ISCAS’85 Benchmarks

15. 15 Asia Test Symposium 2012 For any ISCAS circuit, our method can detect all testable faults in less than 5000 test cycles. Experimental Results – ISCAS’89 Benchmarks Circuit Name #IN|F T | |F HD |/|F T | % ATPG Test SetProposed LFSR Reseeding #TPS max |S| #TP (BIST) #Storage Bits RD % s4203543011.404935539317589.80 s641544673.853353658232481.82 s713545434.243652550527086.11 s8202385010.351001811127925389.00 s8386785716.9278671283380484.62 s95345107911.6886441091445088.37 s14239115013.004189450036490.24 s537821445633.7911220472482149893.75 s9234247647519.31153224172218419988.89 s13207700966428.3924566363418420097.55 s15850611113368.0312158472822427794.21 s3841716643101510.78981455839391331291.84 s385841464347973.87155132054292732096.77

16. 16 Asia Test Symposium 2012 Circuit Name #Storage Bits#TP (BIST)TP Reduction % Ours[1][2]Ours[1][2]([1] - Ours)/[1]([2] - Ours)/[2] c267013983029351082762251598486.7194.83 c755228985175114401450112612311287.1293.73 s420 175385 21039334501767688.6197.78 s641 324216 2205821499364561.1784.03 s713 270216 1655051820579072.2591.28 s820 253138 NA12792916NA56.14NA s838 8041407 87183352351509384.0994.48 s953 450135 2769143159397571.0777.01 s1423 364273 NA5001457NA65.68NA s5378 1498856 1935248242221180841.2178.98 s9234 41994940 66962218137852173183.9189.79 s13207 4200 NA35053418NA8550NA60.02 s15850 4277 NA55082822NA12180NA76.83 s38417 13312 NA349653939NA34510NA88.59 s38584 7320 NA87904292NA8052NA46.70 Avg. 72.5482.62 [1] E. Kalligeros, et al., "An efficient seeds selection method for LFSR-based test-per-clock BIST,“ ISQED, 2002. [2] E. Kalligeros, et al.,"Reseeding-based test set embedding with reduced test sequences," ISQED, 2005. Comparisons – LFSR Reseeding Methods

17. 17 Asia Test Symposium 2012 Comparisons – Mapping-Logic-Based Methods Circuit Name Area overhead (Gate Eqv.)#TP (BIST) Ours[3][4]Ours[3][4] c8806036NA511719NA c135512315NA9081186NA c190813225NA13273327NA c267035037350882710023712 c75527251012462145039588437 s4204412513239318762568 s64181616758210841302 s71368597150519631979 s820631821321279498647 s83820142337683312231435 s953113548391431473114 s14239171585001102929 s537837514397248284694763 s92341050948NA221811207NA Total (c2670 - s5378) 211125031986119832432228886 [3] E. Kalligeros, et al., "On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST," JETTA, 2002. [4] Y. Si, et al., "Multiple test set generation method for LFSR-based BIST," ASP-DAC, 2003.

18. 18 Asia Test Symposium 2012 Circuit Name #Storage Bits#TP (BIST)TP Reduction % Ours[5][6][7]Ours[5][6][7][5][6][7] s420175455315NA393137822365NA71.4898.24NA s641324594324NA582179335316NA67.5498.35NA s713270648432NA505195647088NA74.1898.93NA s820253414253NA1279126011891NA-1.5189.24NA s838804214420771205833646428039510108087.1199.7099.18 s9534508553603519142584327602366064.6397.2196.14 s1423364455NA8245001370NA6752763.50NA99.26 s53781498NA385236552482NA16525081031316NA99.8599.76 s92344199NA1235091732218NA61132503459060NA99.9699.94 s132074200NA140067073418NA19614001805889NA99.8399.81 s158504277NA672135292822NA82197833174908NA99.9799.91 s3841713312NA31616309783939NA10524966436216182NA99.996NA s385847320NA3220887694292NA943372328936379NA99.99599.95 Avg. 60.9996.9599.24 [5] K. Chakrabarty, et al., "Built-in Test Generation For High-Performance Circuits Using Twisted-Ring Counters," VTS, 1999. [6] S. Swaminathan, et al., "On Using Twisted-Ring Counters for Test Set Embedding in BIST," JETTA, 2001. [7] B. Zhou, et al., "Simultaneous reduction in test data volume and test time for TRC-reseeding," GL-VLSI, 2007. Comparisons – TRC-Based Reseeding Methods

19. 19 Asia Test Symposium 2012 Conclusions This paper proposes a new test-per-clock LFSR reseeding algorithm that can simultaneously minimize both the storage data volume and the test sequence length. Experimental results show that  comparing with previous LFSR-based reseeding methods, our method can reduce more than 70% test sequence length with a much smaller number of seeds.  comparing with previous mapping-logic-based BIST methods, our method can save over 50% of test sequence length with comparable area overhead.  comparing with previous TRC-based reseeding methods, 60~99% test sequence length can be reduced by using our method with smaller storage data volume.

20. 20 Asia Test Symposium 2012 Thank You Very Much for Your Attention.

21. 21 Asia Test Symposium 2012 Experimental Results – IWLS industrial circuits Circuit Name #IN|F T | |F HD |/|F T | % #TP (ATPG) Proposed LFSR Reseeding |S| #TP (BIST) RD % tv80542176456.1541821847694.98 mem_ctrl1589214938.7423347793079.83 ac97_ctrl2487304790.38402343295.00 usb_funct2898367765.10885786394.32 pci_bridge323955412177.2313871327794.93 wb_conmax25241232790.762342305499.15 des_perf143932315560.001291892199.22 Avg. 93.92 The results on IWLS industrial circuits are even better than those on ISCAS benchmark circuits because less number of redundant faults 100% stuck-at fault coverage is targeted and the input parameter LCS (limit on the number of consecutive redundant patterns) is set to 60.

22. 22 Asia Test Symposium 2012 Experimental Results – Different LCS values LCS60100200300400 s838 (857 faults) |S||S|128774 #TP (BIST)8331190137523402597 s9234 (6475 faults) |S||S|17141312 #TP (BIST)22182013427981908368 s38584 (34797 faults) |S||S|55433 #TP (BIST)429255177444982215739 LCS value increases → storage test data volume decreases test sequence length increases. 100 stuck-at fault coverage is targeted. LCS: limit on the maximum number of consecutive redundant patterns