ECE 448 – FPGA and ASIC Design with VHDL Lecture 15 External SRAM

2 ECE 448 – FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 10, External SRAM

3 Block diagram of a typical SRAM ECE 448 – FPGA and ASIC Design with VHDL

4 SRAM Functional Table ECE 448 – FPGA and ASIC Design with VHDL

5 SRAM Simplified Functional Table ECE 448 – FPGA and ASIC Design with VHDL

6 Timing diagram of an address-controlled read cycle ECE 448 – FPGA and ASIC Design with VHDL

7 Timing diagram of an output_enable-controlled read cycle ECE 448 – FPGA and ASIC Design with VHDL

8 SRAM Timing Parameters (in ns) ECE 448 – FPGA and ASIC Design with VHDL

9 Timing diagram of write cycle ECE 448 – FPGA and ASIC Design with VHDL

10 SRAM Timing Parameters (in ns) ECE 448 – FPGA and ASIC Design with VHDL

11 Role of a memory controller ECE 448 – FPGA and ASIC Design with VHDL

12 Block diagram of a memory controller ECE 448 – FPGA and ASIC Design with VHDL

13 ASM chart of a safe SRAM controller ECE 448 – FPGA and ASIC Design with VHDL

14 ASM chart of a testing circuit ECE 448 – FPGA and ASIC Design with VHDL

15 ASM chart of an alternative SRAM controller: design I ECE 448 – FPGA and ASIC Design with VHDL

16 ASM chart of an alternative SRAM controller: design II ECE 448 – FPGA and ASIC Design with VHDL

17 ECE 448 – FPGA and ASIC Design with VHDL ASM chart of an alternative SRAM controller: design III

18 Generating a half cycle with DDR ECE 448 – FPGA and ASIC Design with VHDL