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ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL.

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Presentation on theme: "ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL."— Presentation transcript:

1 ECE 448 – FPGA and ASIC Design with VHDL George Mason University ECE 448 Lab 2 Implementing Combinational Logic in VHDL

2 Part 1: Introduction to Lab 2 Implementing Combinational Logic in VHDL. Part 2: Example: miniALU. Part 3: Variable Rotator. Part 4: Hands-on Session: Simulation Using ISim and ModelSim. Part 5: Demos of Lab 1. Agenda for today

3 Part 1 Introduction to Lab 1 Implementing Combinational Logic in VHDL

4 Interface of ALU

5

6 Table of Operations

7 Block Diagram

8 Part 2 Example: Mini ALU Example of a Problem Similar to Task 1

9 opcode A B M R Mini ALU 4 4 4 4 4

10 MnemonicOperationOpcode ADDABR= A + B0000 ADDAMR = A + M0001 SUBABR = A - B0010 SUBAMR = A - M0011 NOTAR = NOT A0100 NOTBR = NOT B0101 NOTMR = NOT M0110 ANDABR = A AND B0111 ANDAMR = A AND M1000 ORABR = A OR B1001 ORAMR = A OR M1010 XORABR = A XOR B1011 XORAMR = A XOR M1100

11 Block diagram

12 Part 3 Variable Rotator Example of a Problem Similar to Bonus Task

13 Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

14 Interface 4 4 2 A B C

15 Block diagram C

16 Fixed Rotation in VHDL A(3) A(2) A(1) A(0) A(2)A(1)A(0)A(3) A<<<1 SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); ArotL <= A(2 downto 0) & A(3); ArotL A

17 Part 4 Hands-on Session Simulation Using ISim and ModelSim

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