1. CEC 220 Digital Circuit Design State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Slide 1 of 13

2. Lecture Outline Friday, April 11 CEC 220 Digital Circuit Design State Machine Charts  Describing state machines using state charts Implementing a State Machine in VHDL Slide 2 of 13

3. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design State Machine (SM) Charts  An alternative to state transition graphs and state transition tables State Box Decision Box Conditional Output Box The three principal components of a SM chart Slide 3 of 13

4. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design The State Machine Block One entrance path Many exit paths Decision boxes Conditional Output boxes (Mealy) One SM block for each state Each SM block is typically NOT unique Slide 4 of 13

5. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design SM blocks are typically NOT unique Pres. State Next StatePres. Output (Z 1 Z 2 ) 0001101100011011 S1  Pres. State Next StatePres. Output (Z 1 Z 2 ) 0001101100011011 S1S2S3S2S311 10  Pres. State Next StatePres. Output (Z 1 Z 2 ) 0001101100011011 S1  Pres. State Next StatePres. Output (Z 1 Z 2 ) 0001101100011011 S1S2S3S2S311 10  Slide 5 of 13

6. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Another example of equivalent SM’s Slide 6 of 13 Multiple active link paths Single active link path

7. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Conversion of a State Graph to a SM Chart Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0 S1 S2 Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0100?? S1010?? S2001?? Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S010000 S101000 S20011000101 Pres. State Next StatePres. Output (Z a Z b Z c Z 1 Z 2 ) 0101 S0 S110000 S1S0S201000 S2S0S20011000101 Slide 7 of 13

8. State Machine Charts Friday, April 11 CEC 220 Digital Circuit Design Examples: Convert the State Graphs to SM Charts Slide 8 of 13

9. Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design State Machine Implementation in VHDL Pres. State Next StatePres. Output (Z) X=0X=1 S0 = 000S2S10 S1 = 001S5S00 S2 = 010S3S10 S3 = 011S3S40 S4 = 100S4S31 S5 = 101S4S00 Slide 9 of 13

10. Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design Define the next state behavior here!! Slide 10 of 13

11. Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design SM in VHDL Slide 11 of 13

12. Implementing a State Machine in VHDL Friday, April 11 CEC 220 Digital Circuit Design Simulation Waveform  VHDL code is online Slide 12 of 13

13. Next Lecture Friday, April 11 CEC 220 Digital Circuit Design A Digital Design Example  Dice game design Slide 13 of 13