1. George Mason University Timing Analysis ECE 545 Lecture 8a

2. 2 Required reading P. Chu, RTL Hardware Design using VHDL Chapter 8.6 Timing Analysis of a Synchronous Sequential Circuit Chapter 16.1 Overview of a Clock Distribution Network Chapter 16.2 Timing Analysis with Clock Skew

3. 3ECE 448 – FPGA and ASIC Design with VHDL Hold & Setup Time Metastability

4. 4 Violation of Hold or Setup Time

5. 5 Response of a Flip-Flop to Timing Violation There exists a third and unstable point of equilibrium between the two stable states representing the binary states 0 and 1 respectively.

6. 6 Points of Equilibrium in Flip-Flops and Latches

7. 7 Patterns of Metastable Behavior

8. 8 Response to Timing Violation

9. 9 Impact on Downstream Circuitry

10. 10ECE 448 – FPGA and ASIC Design with VHDL Clock Skew

11. 11 Clock Skew

12. 12 Clock Skew Map for a Cell Processor

13. 13 Incorrect Clock Tree Layout – Narrow Meander

14. 14 Optimized Clock Tree Layout – H Tree

15. 15 Clock Skew - Summary