1. Timing Analysis ECE 448 Lecture 14
ECE 448 – FPGA and ASIC Design with VHDL

2. Timing Analysis (1)
ECE 448 – FPGA and ASIC Design with VHDL

3. Timing Analysis (2)
d’comb ij
ECE 448 – FPGA and ASIC Design with VHDL

4. Violation of Hold or Setup Time

5. Response of a Flip-Flop to Timing Violation
There exists a third and unstable point of equilibrium
between the two stable states representing
the binary states 0 and 1 respectively.

6. Patterns of Metastable Behavior

7. Response to Timing Violation

8. Impact on Downstream Circuitry

9. Part of a Block Diagram Part of an ASM Chart . . . en_x en_y
Implemented at 100 MHz, clk input is 100 MHz
Implemented at 100 MHz, clk input is 50 MHz

10. Part of a Block Diagram Part of an ASM Chart . . . en_x en_x2 en_x4
en_y
Implemented at 100 MHz, clk input is 100 MHz