1. Lecture 5 Block Diagrams Modes of Operation of Block Ciphers

2. ECE 448 – FPGA and ASIC Design with VHDL Modes of Operation of Block Ciphers

3. Block vs. stream ciphers Stream cipher Internal state - IS Block cipher KK M 1, M 2, …, M n m 1, m 2, …, m n C 1, C 2, …, C n c 1, c 2, …, c n C i =f K (M i )c i = f K (m i, IS i ) IS i+1 =g K (m i, IS i ) Every block of ciphertext is a function of only one corresponding block of plaintext Every block of ciphertext is a function of the current block of plaintext and the current internal state of the cipher

4. Typical stream cipher SenderReceiver Pseudorandom Key Generator mimi plaintext cici ciphertext kiki keystream key initialization vector (seed) Pseudorandom Key Generator mimi plaintext cici ciphertext kiki keystream key initialization vector (seed)

5. Standard modes of operation of block ciphers Block cipher turned into a stream ciphers ECB mode Counter mode CFB mode CBC mode

6. ECB (Electronic CodeBook) mode

7. Electronic CodeBook Mode – ECB Encryption M1M1 M2M2 M3M3 E C i = E K (M i ) for i=1..N M N-1 MNMN E E EE... C1C1 C2C2 C3C3 C N-1 CNCN K K K K K

8. Electronic CodeBook Mode – ECB Decryption C1C1 C2C2 C3C3 D M i = D K (C i ) for i=1..N C N-1 CNCN D D DD... M1M1 M2M2 M3M3 M N-1 MNMN K K K K K

9. Electronic CodeBook Mode – ECB (simplified block diagram) E K IN OUT CiCi MiMi D K IN OUT CiCi MiMi C i = E K (M i ) M i = D K (C i )

10. Electronic CodeBook Mode – ECB (combined block diagram) E K IN OUT D K IN OUT bdo bdi bdi = M i for Encryption C i for Decryption bdo = C i for Encryption M i for Decryption

11. Counter Mode

12. Counter Mode - CTR Encryption m1m1 m2m2 m3m3 E c i = m i  k i k i = E K (IV+i-1) for i=1..N m N-1 mNmN... E E EE c1c1 c2c2 c3c3 c N-1 cNcN IVIV+1 IV+2 IV+N-2 IV+N-1 k1k1 k2k2 k3k3 k N-1 kNkN K K K K K

13. Counter Mode - CTR Decryption c1c1 c2c2 c3c3 E m i = c i  k i k i = E K (IV+i-1) for i=1..N c N-1 cNcN... E E EE m1m1 m2m2 m3m3 m N-1 mNmN IVIV+1 IV+2 IV+N-2 IV+N-1 k1k1 k2k2 k3k3 k N-1 kNkN K K K K K

14. Counter Mode – CTR (simplified block diagram) E K IN OUT counter IV cici mimi E K IN OUT counter IV cici mimi IS 1 = IV c i = E K (IS i )  m i IS i+1 = IS i +1 IS 1 = IV m i = E K (IS i )  c i IS i+1 = IS i +1 IS i

15. Counter Mode – CTR (combined block diagram) E K IN OUT counter IV bdo bdi IS i bdi = m i for Encryption c i for Decryption bdo = c i for Encryption m i for Decryption

16. CFB (Cipher FeedBack) Mode

17. Cipher Feedback Mode - CFB Encryption m1m1 m2m2 m3m3 E m N-1 mNmN... E E EE c1c1 c2c2 c3c3 c N-1 cNcN IV c i = m i  k i k i =E K (c i-1 ) for i=1..N, and c 0 = IV k1k1 k2k2 k3k3 k N-1 kNkN

18. Cipher Feedback Mode - CFB Decryption m1m1 m2m2 m3m3 E m N-1 mNmN... E E EE c1c1 c2c2 c3c3 c N-1 cNcN IV m i = c i  k i k i =E K (c i-1 ) for i=1..N, and c 0 = IV k1k1 k2k2 k3k3 k N-1 kNkN

19. Cipher Feedback Mode – CFB (simplified block diagram) E K IN OUT cici mimi E K IN OUT cici mimi IV IS 1 = IV c i = E K (IS i )  m i IS i+1 = c i IV IS i register IS 1 = IV m i = E K (IS i )  c i IS i+1 = c i

20. Cipher Feedback Mode – CFB (combined block diagram) E K IN OUT bdo bdi IV IS i register bdi = m i for Encryption c i for Decryption bdo = c i for Encryption m i for Decryption bdi

21. CBC (Cipher Block Chaining) Mode

22. Cipher Block Chaining Mode - CBC Encryption m1m1 m2m2 m3m3 E IV c i = E K (m i  c i-1 ) for i=1..N c 0 =IV m N-1 mNmN... E E EE c1c1 c2c2 c3c3 c N-1 cNcN

23. Cipher Block Chaining Mode - CBC Decryption m i = D K (c i )  c i-1 for i=1..N c 0 =IV m1m1 m2m2 m3m3 m N-1 mNmN IV... D D D DD c1c1 c2c2 c3c3 c N-1 cNcN

24. Cipher Block Chaining Mode – CBC (simplified block diagram) E K IN OUT cici mimi D K IN OUT cici mimi IV IS 1 = IV c i = E K (IS i  m i ) IS i+1 = c i IS 1 = IV m i = D K (c i )  IS i IS i+1 = c i IV IS i register

25. Cipher Block Chaining Mode – CBC (combined block diagram) E K IN OUT D K IN OUT IV IS i register cici bdi bdo bdi

26. ECE 448 – FPGA and ASIC Design with VHDL Advanced Encryption Standard (AES) Pseudocode

27. AES Encryption

28. AES Decryption

29. ECE 448 – FPGA and ASIC Design with VHDL AES: Symbols, Block Diagrams, Interfaces

30. AES_Enc Encryption Only Key scheduling done as a part of initialization

31. Symbol

32. Block Diagram – AES_Enc

33. Block Diagram – Round

34. Block Diagram – KeyUpdate

35. AES_Enc: Interface with the Division into the Datapath and Controller

36. AES_Enc_KOF Encryption Only Key scheduling done On the Fly

37. Symbol

38. Block Diagram – AES_Enc_KOF

39. Block Diagram – Round

40. Block Diagram – KeyUpdate

41. AES_Enc_KOF: Interface with the Division into the Datapath and Controller

42. AES_EncDec Encryption and Decryption Key scheduling done as a part of initialization

43. Symbol

44. Block Diagram – AES_EncDec

45. Block Diagram – Round

46. Block Diagram – InvRound

47. Block Diagram – KeyUpdate

48. AES_EncDec: Interface with the Division into the Datapath and Controller

49. ECE 448 – FPGA and ASIC Design with VHDL Example of a Hierarchical Block Diagram JH hash function

50. Top Level

51. R8/R6

52. L

53. ECE 448 – FPGA and ASIC Design with VHDL Example of a Hierarchical Block Diagram BLAKE hash function

54. Top Level

55. Permute8

56. Core8

57. G_mod

58. ECE 448 – FPGA and ASIC Design with VHDL Interface of CipherCore Datapath

59. 59 Block Diagram of AEAD

60. Input Ports (nonce, IV) (only few candidates) (AD, M, C) (we will not use it)

61. ECE 448 – FPGA and ASIC Design with VHDL Timeline

62. Thursday 10/15, 12 noon: First draft of block diagrams (Blackboard) Thursday 10/15, 1:00-4:30pm Friday 10/16, 1:00-8:00pm Discussion of draft block diagrams (30 minutes per person, 60 minutes per group, electronic sign-up using Doodle) Project Timeline: Draft Block Diagrams

63. Thursday 10/22, 12 noon Revised block diagrams due (Blackboard) Thursday 10/22, 1:00-4:30pm Friday 10/23, 1:00-8:00pm Discussion of revised block diagrams (30 minutes per person, 60 minutes per group, electronic sign-up using Doodle) Project Timeline: Revised Block Diagrams