Uli Schäfer 1 JEM Test Strategies Current plan: no JTAG tests at R&S  initial tests done at MZ Power-up / currents Connectivity tests (JTAG) per (daughter)

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Presentation transcript:

Uli Schäfer 1 JEM Test Strategies Current plan: no JTAG tests at R&S  initial tests done at MZ Power-up / currents Connectivity tests (JTAG) per (daughter) module Signal integrity: DCI / 1 test pin per bank, scope Interface tests w. firmware pattern detection per module (?), per JEM System tests w. simulation and S/W comparison, per crate (MZ, RAL??) Full system test, 2 crates, PPR/ROS (  commissioning)

Uli Schäfer 2 1.LVDS in 2.SMM out 3.JMM out 4.DAQ 5.ROI 6.FIO VME, CAN,TTC, JTAG, diagnostic clock out JEM Interfaces

Uli Schäfer 3 JEM Test Setup Power-up, JTAG: Lab equipment available(?) Pod available (want another, USB based?) S/W : Tools available, test vectors to be written (BB/NN) Test adapters : design under way (status?), separate adapters required for main board (CM,RM,IM,BPL,CF,TTCdec), input modules, ?? Interface tests : High rate, F/W pattern detection where possible S/W filling playback (and comparison) memories and reading out error counters

Uli Schäfer 4 JEM Test Resources Setup: signal source  JEM  sink Sources: DSS (available, 16 ch., buffers ~64k deep ?) LSM 96ch. (to be supplied by B’ham soon?, ~ k deep) PPr schedule unclear (components for first 4 PPMs available soon ? LCD status? 128 deep?) Playback memories (256 deep, circular buffers) Do we want to have standalone 24-ch. Input daughter tester ? Sinks – pattern detection: no per-event readout; counters only – internal spy (256 deep, circular buffers): Jet FIO spy JMM spy ? ROI spy ? SMM spy DAQ spy (L1A triggered !)

Uli Schäfer 5 JEM Test Resources External sinks At RAL: CMM / ROD / ROS (no spy  L1A-triggered) ROD / ROD emulator (spy ?-deep) CMM spy (128-deep) CMM parity check (counters) Any new test adapter to be built ? We will have a mixture of non-event related counter readout, circular buffer readout from spy memories and L1A-triggered readout. How do we set up the timing / how do we feed the simulation / comparison with the proper time slices ?

Uli Schäfer 6 JEM Test baseline Interface tests Supported sources Supported sinks System tests Supported sources Supported sinks Who will define aggressive test patterns ? Any specific software required for final tests beyond full-crate tests ? Time scale ?