Uli Schäfer JEM0 Status (summary) 3 JEM0s up and running: JEM0.0 used for standalone tests only (Mainz) JEM0.1 fully qualified module0 JEM0.2 (like JEM0.1.
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Presentation on theme: "Uli Schäfer JEM0 Status (summary) 3 JEM0s up and running: JEM0.0 used for standalone tests only (Mainz) JEM0.1 fully qualified module0 JEM0.2 (like JEM0.1."— Presentation transcript:
Uli Schäfer JEM0 Status (summary) 3 JEM0s up and running: JEM0.0 used for standalone tests only (Mainz) JEM0.1 fully qualified module0 JEM0.2 (like JEM0.1 but main=XCV1600E) JEM0.1 and JEM0.2 currently under test at RAL Hardware fully assembled and tested, apart from CAN and flash configurator. Firmware near-final apart from jet code integration and ROI Continue to improve HDL code (Andrea)
Uli Schäfer JEM1 : Re-design JEM1 : increased routing density due to new packages used on FPGAs (Virtex-II) and de-serialisers. Xilinx reference layout not applicable to large and thick PCBs due to requirements on precision of via position. Use daughter modules on JEM1 for Input stage (de-serialiser and input processor) TTC ROC Mini-review at RAL in December, 2002 Bruno currently working on input module
Uli Schäfer JEM Main Processor Input Processor 15* '921260 88 LVDS links 6 links per de-serialiser Config VME ROC TTC G G 15 x 6-channel de- serialisers : SCAN921260 4 Input Processors : XC2V1500 Main Processor XC2V2000 DCS 6 VME
Uli Schäfer JEM1 :PCB design issues De-serialisers, TTCrx and XC2V are fBGAs with virtually no unused pins. 3 supply voltages (digital, analog, PLL) on de-serialisers. High density of vias V CC /GND planes perforated need small vias, low clearances from via to GND/V CC high accuracy required PCB thickness increased to 2mm (compatibility) Small via diameters not possible with thick PCBs We need high V CC /GND distributed capacitance thin FR4 sheets/prepreg (shrinkage) reduced accuracy
Uli Schäfer JEM1 Due to PCB issues, work on schematics has been discontinued and layout of a sub-set of the schematics was started: Preliminary layout of input block with 4 de-serialisers and one input FPGA is under way and is being discussed with the PCB manufacturer (Andus). cost, technology (blind vias, micro vias,..?), timescale Fallback solution: old-style JEM 1.6mm, daughter boards ? Even though there won‘t be large amounts of (ATLAS) money spent on the first batch of JEM1s, a review will be appropriate due to technological challenges.
Uli Schäfer JEM1 First feedback from PCB manufacturer: We share our problems with everyone using modern fBGA devices with full ball array as opposed to ring of balls. Urged to go to 1.6mm PCB. It is no problem to have thicker board edges that fit the rails. Mechanical structures within a PCB are standard technology. Even integrated stiffeners are possible, if required. With 1.6mm thickness 250 µm vias are possible. We are guaranteed to have 150µm of metal between two 1mm spaced vias. Recommendation for power planes: use GND/V CC /GND sandwiches throughout to increase distributed capacitance.
Uli Schäfer Full slice test Slice test will take place in x/2003 JEM0.1 is available now JEM0.2 is under production now 1-2 JEM(s)0 will be submitted in (x-2.5)/2003 Have JEMs1.0 available in ongoing slice test at a later stage JEM1 seriously different from JEM0, expect minor PCB revisions (JEM1.1) for production modules
Uli Schäfer List of Modifications JEM0 JEM1 Replace de-serialisers by compatible 6-channel devices with B/Scan facility. Allow for use of redundant channel to reduce the need for re-work of the de- serialiser BGAs Replace 11 input FPGAs (8-channels each) by 4 Virtex-II chips Reduce board routing complexity and improve serviceability by using input daughter modules (24channels each) Make input FPGA control path (VME) compatible to the one used on JEM0.0 main processor (point-to-point, no ring bus) Widen on-board VME control paths slightly Replace main processor by larger Virtex II in 1.27mm BGA package Use 1.5V signalling where possible (previously 2.5V) Use internal source termination ( DCI ) on all signals (was discrete source termination on JEM0) Provide the ROC with full access to TTCrx Widen TTC/DAQ paths to the processors slightly Move TTC control and clock mirror into ROC Replace all CPLDs by a single FPGA configured from flash memory Add parallel flash memory for processor configuration (CP style) Make CAN H/W identical to CP (Fujitsu)
Uli Schäfer Input Module Module size: 60x60mm Connector (Bottom) Input Processor 6-ch deser. LVDS diff. FIO Main Control