CMOS Technology: How are chips fabricated? EE116B (Winter 2004): Lecture #2

References for this Lecture http://vlsi.wpi.edu/webcourse/ch02/ch02.html “How chips are made” – Intel http://www.intel.com/education/teachtech/learning/chips/index.htm “Microelectronics 101” – IBM http://www-3.ibm.com/chips/bluelogic/manufacturing/makechip/ [Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Ingredients of Chip Making Silicon Wafers cut from an ingot of pure silicon, are used by Intel to make microprocessors. Silicon, the primary ingredient of beach sand, is a semiconductor of electricity. Semiconductors are materials that can be altered to be either a conductor or an insulator. Chemicals and gases are used throughout the chip-making process. Some, like hexamethyldisilazane, are complex and difficult to pronounce. Others, such as boron, are simple elements found in the Periodic Table of the Elements. Metals, such as aluminum and copper, are used to conduct the electricity throughout the microprocessor. Gold is also used to connect the actual chip to its package. Ultraviolet (UV) Light has very short wavelengths and is just beyond the violet end of the visible spectrum. UV light is used to expose patterns on the layers of the microprocessor in a process much like photography. Masks used in the chip-making process are like stencils. When used with UV light, masks create the various circuit patterns on each layer of the microprocessor. [Courtesy Intel. Adapted from http://www.intel.com/education/teachtech/learning/chips/preparation.htm]

How is CMOS built? Start with a disk of silicon called wafer 75 mm to 230 mm in diameter, < 1 mm thick cut from ingots of single-crystal silicon pulled from a crucible of pure molten polycrystalline silicon using a seed crystal Different processing steps and techniques Introduce dopants Oxidation Masking Polysilicon

Introduce Dopants Pure silicon is a semiconductor bulk electrical resistance in between that of a conductor and insulator Conductivity of silicon can be varied several orders of magnitude by introducing impurity atoms called dopants acceptors: accept electrons to leave holes in silicon lead to p-type silicon (e.g. Boron) donors: provide electrons to silicon lead to n-type silicon (e.g. Arsenic, Phosphorous)

Introduce Dopants (2) Deposition through diffusion Ion Implantation evaporating dopant material into the silicon surface thermal cycle: impurities diffuse deeper into material Ion Implantation silicon surface subjected to highly energized donor or acceptor atoms atoms impinge silicon surface, and drive below it to form regions of varying concentrations Epitaxy growing a single-crystal film on the silicon surface silicon wafer subjected to elevated temperatures and a source of dopant material Ion Implantation

Oxidation Method 1: Heating silicon wafers in an oxidizing atmosphere (O2 or H2O) Consumes Si Grows equally in both vertical directions Method 2: Deposition Deposited on top of existing layers

Masking Masks act as barrier against e.g. Commonly used mask materials ion implantation dopant deposition before diffusion (dopants do not reach surface) oxidation (O2 or H2O does not reach surface) Commonly used mask materials photoresist polysilicon silicon dioxide (SiO2) silicon nitride (SiN)

Example: oxide mask bare silicon wafer oxidize wafer deposit layer of photoresist expose the photoresist selectively to UV light The drawn mask pattern determines which part is exposed Resist polymerizes where exposed

unexposed resist is removed with solvent: negative resist (positive resist: exposed resist is removed) exposed oxide is etched photoresist is washed off the oxide can now be used as a masking layer for ion implantation UV lithography: line width limited by diffraction and alignment tolerances, but tricks are used Electron beam lithography has emerged: directly from digital data, but more costly and slow

Polysilicon Silicon also comes in a polycrystalline form Used as called polysilicon, or just poly high resistance normally doped at the same time as source/drain regions Used as an interconnect in silicon ICs gate electrode in MOS transistors most important: acts as a mask to allow precise definition of source and drain extension under gate minimum gate to source/drain overlap improves circuit performance (why?) called self-aligned process

Construction of Transistors Depends on ability to control what type  dopant source how many  energy, time, temperature etc. where  using special material as “masks” of impurities are introduced into silicon wafer

Simplified View of CMOS Fabrication Process

A Basic N-well CMOS Process Create oxide mask (see slide 8) using the well-mask Implant the N-well Etch away the oxide mask Grow the thin oxide (gate oxide) over the entire wafer Deposit a SiN (nitride layer) and pattern it with the mask for the active areas (n and p diffusion): defines where the transistors will be

Etch away the oxide where it is exposed Deposit resist patterned by the well-mask Channel stop implants: make substrate more p+ (why?) (active areas are protected by the nitride-oxide layer)

Remove resist and grow field oxide (nitride protects the thin oxide) Etch nitride Deposit polysilicon Apply photoresist with poly-mask and etch poly

Use n+ mask to leave only the regions where nmos tors are wanted free (also called the select mask) Implant the n dopants: self-aligned process Channel is masked from S and D by the gate Poly is also implanted (needed to improve conductivity) Remove masking material

Remark: sometimes more complex S/D structures are used (LDD: lightly doped drain) Complementary of n+ mask is used to define p+ areas

Oxide deposition Apply resist using contact-mask and etch contact holed Deposit metal Apply resist using metal-mask and etch metal interconnects

Repeat steps q-t for multiple metal layers Passivate wafer (protect again environment, contaminants) Etch openings for bonding pads to allow for connection to the package

CMOS Inverter in N-well Process

Substrate & Well Contacts In N-well process p-type substrate is connected to VSS p+ regions well is connected to VDD n+ regions Called: well contacts substrate contacts

Latch-up

Latch-up (contd.)

Guard Rings

P-well Process P-well processes were common in early days N-well is more popular now P-well preferred where NMOS and PMOS characteristics need to be more balanced transistor that resides in well tends to have inferior characteristics as compared to transistor in native substrate P-well has better PMOS than a N-well process

Twin-Well Processes Allow separate optimization of NMOS and PMOS independent optimization of threshold voltage, body effect, gain, etc.

Silicon on Insulator Insulating substrate (e.g. sapphire) Advantages no latch-up problems speed due to lower parasitic substrate capacitance closer packing of NMOS and PMOS transistors power advantage: no leakage current

CMOS Process Enhancements for Better Interconnect Process enhancements to ease routing, especially automated routing improve power and clock distribution Enhancements include: additional layers of metal (2,3, or more) additional layers of poly (2, 3, or more) improving existing layer of poly reduce sheet resistance of poly (20-40 ) by combining it with a refractory metal (e.g. silicon & tantalum) improving existing layer of metal copper instead of aluminum

Two-level Metal Process Normally Aluminum is used for metal layers As vertical topology becomes more varied, the width and spacing of conductors has to increase to avoid conductors becoming too thin, and hence break, at vertical topology jumps

Two-level metal Via/Contact Geometries Via to connect M1 & M2 Separation between via & contact to diff or poly M1 must be involved in contact to diff or poly M1 & M2 borders required around via Restrictions on placement of via

Polysilicon/Refractory Metal Interconnect Goal is to allow the gate material to be used as a moderate long-distance interconnect

Advanced Metallization Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

CMOS Layout Rules scalable design rules: lambda parameter Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Example CMOS Layout Rules

Example CMOS Layout Rules (contd.)

Example CMOS Layout Rules (contd.)

CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Select (p+,n+) Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Layers in 0.25 mm CMOS process Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Intra-Layer Design Rules 4 Metal2 3 Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Transistor Layout Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Vias and Contacts Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Select Layer Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

CMOS Inverter Layout Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Layout Editor Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Sticks Diagram 1 V 3 In Out GND Dimensionless layout entities Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program Adapted from Digital Integrated Circuits (2nd Edition). Copyright 2002 J. Rabaey et al."

Future of IC Technology? L. Geppert. The amazing vanishing transistor act. IEEE Spectrum, October 2002. pp. 28-33. http://eewww.eng.ohio-state.edu/~berger/press/spectrum_cmos_trends.pdf R.D. Isaac. The future of CMOS technology. IBM Journal of Research & Development, May 2000. pp. 369-378. http://www.research.ibm.com/journal/rd/443/isaac.html T.H. Lee.A vertical leap for microchips. Scientific American, January 2002. http://www.sciam.com/article.cfm?colID=1&articleID=000BD05C-D352-1C6A-84A9809EC588EF21 Beyond transistors: organic, molecular, quantum …

N-well CMOS Design Rules

N-well CMOS Design Rules (contd.)

N-well CMOS Design Rules (contd.)

N-well CMOS Design Rules (contd.)

N-well CMOS Design Rules (contd.)

N-well CMOS Design Rules (contd.)

N-well CMOS Design Rules (contd.)

CMOS Inverter in N-Well

CMOS Inverter in N-Well

CMOS Inverter in N-Well

Merged or Abutting Substrate Contact