1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew B. Kahng, Hailong Yao University of California, San Diego
Outline Background Main Contributions LP-Problem Formulation Experimental Results Conclusion 2 UCSD VLSI CAD Laboratory ISQED-2009
3 Background Sizing problem –Knobs to optimize power, timing and area Vdd, Vth, L gate, W gate, etc. –Find optimal sizing for tradeoff of power, timing and area Basic idea of leakage optimization –High speed (high leakage) gates critical paths –Low speed (low leakage) gates non-critical paths Previous works on leakage optimization –Iterative optimization local optimum –Simplified timing model timing violations
Contributions Key difference from previous work –Detailed delay modeling with signoff timing analysis –on per-timing-arc / per-instance –to capture local delay sensitivity accurately –High-speed and high-quality linear programming (LP) Key applications of LP-framework Leakage power minimization under timing constraints Simultaneous timing legalization with leakage minimization 4 UCSD VLSI CAD Laboratory ISQED-2009
5 Cell Delay Model SPICE simulations –65GP technology –All timing arcs –Rise and fall –7 input slew x 7 load –More than 50 cell masters –Gate length from 50nm to 75nm Cell delay is approximately linear in gate length Delay vs. gate length (A1 to Y in 2-input AND) d: cell delay L g : gate length , : calibrated coefficients for each timing entry
Circuit Delay Model Directed acyclic graph (DAG) representation –Cell vertex –Wire edge –Super source S and super sink T 6 UCSD VLSI CAD Laboratory ISQED-2009 Delay variables d v u : cell delay w u,v : wire delay a v : arrival time to node v Delay constraint Flip-flop A Flip-flop B Q u v D S CK T
7 UCSD VLSI CAD Laboratory ISQED-2009 LP for Leakage Power Optimization Objective: −Maximize weighted sum of gate lengths ( Minimize leakage power) without degrading circuit performance D: max. delay minL v : min. gate length maxL v : max. gate length v : Power / Delay
8 UCSD VLSI CAD Laboratory ISQED-2009 LP for Timing Legalization Objective: −Given a design with timing violations, −Improve the worst negative slacks of the design with minimum leakage increase D: min. delay bound : scaling parameter minL v : min. gate length maxL v : max. gate length v : Power / Delay
9 UCSD VLSI CAD Laboratory ISQED-2009 Timing and Leakage Optimization Flow Cell libraries Coefficients calibration LP-Solver Netlist + Parasitic + Timing const. Slew / Load / DelayTiming Graph LP-Generator Cell Swapping New Netlist Timing / leakage analysis Timing and leakage report
10 UCSD VLSI CAD Laboratory ISQED-2009 Experimental Setup Test case: 65nm technology Library preparation –65GP from TSMC (L gate = 60nm) –Multi-L gate libraries: 50nm, 60nm, 70nm –L gate biasing: 55nm, 56nm, …, 65nm –Naming convention: e.g., L60 L gate 60nm Delay and leakage evaluation –RC extraction:Synopsys STAR-RCXT (v ) –Delay: Synopsys PrimeTime (v ) –Leakage power: Cadence SOC Encounter (v5.2) Comparison –Synopsys Astro (v SP5) / Cadence SOC Encounter (v5.2)
11 UCSD VLSI CAD Laboratory ISQED-2009 Leakage Optimization with L gate -Biasing Inputs –Initial design with L60 –L gate biased libraries: from L55 to L65 Outputs –Meet timing –Better leakage –8X 16X faster runtime than SOCE SOCE AstroLP SOCEAstroLP SOCE AstroLP
12 UCSD VLSI CAD Laboratory ISQED-2009 Leakage Optimization with Multi-L gate Inputs: –Initial design with L60 –Multi-L gate libraries: L50, L60 and L70 Outputs –Meet timing –Better leakage –5X 14X faster than SOCE SOCE AstroLP SOCEAstroLP SOCE AstroLP
13 UCSD VLSI CAD Laboratory ISQED-2009 Timing Legalization with L gate Biasing Inputs –Initial design with L60 –SOCE leakage optimization worsen timing slack –L gate biased libraries: from L55 to L65 Outputs –Turn timing slacks back or even better –Still obtains smaller leakage power than original
14 UCSD VLSI CAD Laboratory ISQED-2009 Timing Legalization with Multi-L gate Inputs –Initial design with L60 –SOCE leakage optimization worsen timing slack –Multi-L gate libraries: L50, L60 and L70 Outputs –Turn timing slacks back or even better –Still obtains smaller leakage power than original
15 UCSD VLSI CAD Laboratory ISQED-2009 Conclusion and Ongoing Work We revisited and implemented LP-based frameworks –Leakage power minimization and timing legalization Compared with commercial tools, our work shows –Always meet timing –Better leakage power –~10X faster runtime Our methods enable very fast, high-quality power-delay tradeoff estimation and optimization Ongoing work –Larger industrial testcases –Multi-V th, multi-L gate and L gate -biasing –Timing margin and don't-touch methodologies, –Hold time –Multi-mode/multi-corner analysis –dynamic/total power constraints
THANK YOU 16 UCSD VLSI CAD Laboratory ISQED-2009