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Toward PDN Resource Estimation: A Law of General Power Density Kwangok Jeong and Andrew B. Kahng

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Presentation on theme: "Toward PDN Resource Estimation: A Law of General Power Density Kwangok Jeong and Andrew B. Kahng"— Presentation transcript:

1 Toward PDN Resource Estimation: A Law of General Power Density Kwangok Jeong and Andrew B. Kahng (kjeong@ucsd.edu, abk@ucsd.edu)kjeong@ucsd.eduabk@ucsd.edu VLSI CAD Laboratory University of California San Diego

2 UCSD VLSI CAD Laboratory - June 5, 2011(2/18) Outline Power and technology trend Early stage PDN estimation Power law of power density Data collection: random activity distribution Model 1: empirical activity density model Model 2: analytical power density model Toward PDN resource estimation Conclusion

3 UCSD VLSI CAD Laboratory - June 5, 2011(3/18) Power and Technology Trends Power trend and required impedance scaling Frequency increases Power increases Vdd decreases Current increases Required impedance decreases YearLgate (nm) Freq. (GHz) Vdd (V) Power (W) I (A) Z (m  ) 2011246.40.9389.896.59.64 2015178.50.81123.1152.05.33 202010.712.40.68141.8208.63.26 20247.416.60.60170.5284.22.11 ITRS 2010 MPU

4 UCSD VLSI CAD Laboratory - June 5, 2011(4/18) Need for Early PDN Estimation and Synthesis When we have enough information… Placement information Power consumption of gates Stimuli for realistic worst operation  PDN can be designed with detailed information At the early design stage, when we do not have enough information… Expected (average/worst) power of a functional block Rough estimate of area of the functional block  Still need to estimate PDN resources to plan interconnect stack, chip size, bump pitch, etc. considering routing congestion increase due to PDN

5 UCSD VLSI CAD Laboratory - June 5, 2011(5/18) PDN Design at the Early Design Stage Evenly distributed sourcesA single source at center Traditional procedure Decide mesh pitch (and/or width)  Assign current sources  Refine mesh width Current source distribution Given a current consumption (I expected ) I expected / N I expected Too optimistic! Too pessimistic! N: #nodes What is realistic current distribution?

6 UCSD VLSI CAD Laboratory - June 5, 2011(6/18) Trend of Power Density Exponential dependency of power density to area What is the general property of the activity density? Block levelChip levelDevice level AF=7.5% unit area count (J) 1.4e+3 Current density (A/cm 2 ) 1.2e+3 1.0e+3 0.8e+3 0.6e+3 0.4e+3 0.2e+3 0.0e+0 05101520253035404550

7 UCSD VLSI CAD Laboratory - June 5, 2011(7/18) Activity Density Activity density = activity count within a window Correlated with power density What is the maximum activity density? Sampling window (m x m) Die (N x N) Activity at t=1 Activity at t=2 Activity at t=3 Activity at t=T Activity density changes with respect to window size and locations Activity density changes with respect to time

8 UCSD VLSI CAD Laboratory - June 5, 2011(8/18) Normalized Maximum Activity Density Artificial activity distribution Given N  N grids and average activity factor p, Randomly assign activity 1 to p  N  N grids out of N  N grids Maximum activity density for m = 1 to N c(m)  maximum #activity enclosed by m  m area d(m)  c(m) / m 2 for m = 1 to N d norm (m)  d(m) / d(N) Activity density is not a constant N= 5, p=0.2 c(1) = 1  d(1) = 1.00  d norm (1) = 5.00 c(2) = 2  d(2) = 0.50  d norm (2) = 2.50 c(3) = 3  d(3) = 0.33  d norm (3) = 1.32 c(4) = 4  d(4) = 0.25  d norm (4) = 1.25 c(5) = 5  d(5) = 0.20  d norm (5) = 1.00

9 UCSD VLSI CAD Laboratory - June 5, 2011(9/18) Normalized Power Density in a Real Design Testcase: sparc_exu_alu (in OpenSparcT1) #instance: 3k Core size: 130um x 130um Power estimation flow Synthesis: Synopsys Design Compiler Place&route: Cadence SoC Encounter System-level simulation: VirtuTech SIMICS Gate-level simulation: Cadence NC Verilog Power estimation: Synopsys PrimeTime-PX Among 1M cycles, top-1000 high power cycles are collected Power assignment Divide core area into 100 x100 grids Assign the power of each cell to the corresponding grid, based on the cell location d norm (m) m (a) Single cycle (b) Multiple cycles (for w-timeframes) d norm (m) m Linear in a log-log plot  Existence of power law

10 UCSD VLSI CAD Laboratory - June 5, 2011(10/18) Activity Count Calculation Massive data collection for activity count statistics using a dynamic programming approach Parameters to change: - Switching activity (p): 0.05, 0.10, 0.15, 0.25, 0.50, 0.90 - Trial (k): 50 - #Timeframes (w): 1, 2, 4, 8, 32 - Window size (m): 1, 2, …, 100 for x = 1 to N for y = 1 to N CA[ x ][ y ][ 1 ] = CountInBox1(x,y) for m = 2 to N for x = 1 to N for y = 1 to N if ( m == even ) lb  CA[ x ][ y ][ m/2 ] lt  CA[ x ][ y+m/2 ][ m/2 ] rb  CA[ x+m/2 ][ y ][ m/2 ] rt  CA[ x+m/2 ][ y+m/2 ][ m/2 ] CA[ x ][ y ][ m ]  lb + lt + rb + rt else lb  CA[ x ][ y ][ m/2 ] lt  CA[ x ][ y+m/2 ][ m/2+1 ] rb  CA[ x+m/2 ][ y ][ m/2+1 ] rt  CA[ x+m/2+1][ y+m/2+1 ][ m/2 ] cn  CA[ x+m/2 ][ y+m/2 ][ 1 ] CA[x][y][m]  lb + lt + rb + rt - cn (x,y) m = 3 CA[x][y][3] = 1 lt lb rt rb lt lb rt rb cn

11 UCSD VLSI CAD Laboratory - June 5, 2011(11/18) Activity Density from Random Distributions Single timeframeMultiple timeframes Normalized activity density: d norm (m) Sample window size: m Log (m) P = 0.90 Log (d norm (m)) Log (m) P = 0.05 Summary of characteristics  Exponential decay with m  m=1 and w = 1  d norm (w) = 1/p  Large m  d norm (w) = 1  Large w  small d norm (w)  Large p  small impact of w  Small p  large impact of w

12 UCSD VLSI CAD Laboratory - June 5, 2011(12/18) Empirical Activity Density Model Model function is determined to capture the characteristics of the observed activity density Model coefficients are found using fitting with measured data Summary of characteristics  Exponential decay with m  m=1 and w = 1  d norm (w) = 1/p  Large m  d norm (w) = 1  Large w  small d norm (w)  Large p  small impact of w  Small p  large impact of w Exponential decay due to m For small p (~ 0), impact of w is large, and for large p (~1), impact of w is small m = 1 and w =1  d norm (m) = 1/p Large m  d norm (m) = 1 Slow decay due to w

13 UCSD VLSI CAD Laboratory - June 5, 2011(13/18) Model Validation – Empirical Model Model accuracy for all data points Average error: 6.14%, Maximum error: 40.15% d norm (m) m m m m m m m

14 UCSD VLSI CAD Laboratory - June 5, 2011(14/18) Analytical Modeling from Chernoff Bound Fact 1 (Chernoff Bound): Let x 1,…, x n be mutually independent 0/1 random variables, each equal to 1 with probability p. If for any 0 <  < 1, then Let s ij be a 0/1 random variable denoting activity at ( i, j ) We find maximum activity count in rectangles of size m  m whose top-right corner is (u,v)  (of in Chernoff bound) = pm 2,

15 UCSD VLSI CAD Laboratory - June 5, 2011(15/18) Analytical Activity Count Model From Chernoff bound, maximum activity count is bounded as: For a single timeframe: For a multiple timeframes: with probability at least 1 - 

16 UCSD VLSI CAD Laboratory - June 5, 2011(16/18) Model Validation – Analytical Model Model We find model coefficient  for various  values Validation using all data points used in empirical model construction For all  values,  is near 1  tight estimate When cases m < 10 are removed, avg (max) error  3.17%~ 4.88% (23.77%~41.60%)  (given)  (found) Average Error (%) Max Error (%) 0.0010.888411.69656.69 0.010.900310.46615.95 0.10.91329.08570.10 0.20.91738.63555.05 0.50.92298.01534.12 0.90.92667.60519.99

17 UCSD VLSI CAD Laboratory - June 5, 2011(17/18) 100mA (100x100) I = I = 100mA Preliminary Results for PDN Design IR-drop comparison for a fixed power mesh 1mm 2 region consuming 100mA Mesh width = 2um, mesh pitch = 10um PDN resource comparison for a fixed 5% voltage drop 1mm 2 region consuming 100mA Mesh pitch: 10um Uniform Power law (p=0.001) Center UniformPower LawCenter Mesh width1.27 (um)1.49 (um)2.93 (um) Mesh area (VDD+VSS)25.4 (%)29.8 (%)58.6 (%) Max drop: 31.7mV Max drop: 73.0mV Max drop: 37.4mV

18 UCSD VLSI CAD Laboratory - June 5, 2011(18/18) Conclusions and Ongoing Works We have presented a general law for power density We provide closed-form activity density models from empirical data analysis and probability theory  These can be used to improve the accuracy and efficiency of early-stage PDN resource prediction Our ongoing work Further simplification of models Validation against large industry designs Development of fast and accurate PDN design and optimization methodologies for early stages of IC design

19 THANK YOU!

20 BACKUP

21 UCSD VLSI CAD Laboratory - June 5, 2011(21/18) benchmark binary - bzip, equak,... (SPEC-2000) system-level simulation Simics + Transplant RTL design OpenSPARC T1 benchmark analysis SimPoint reprehensive execution phase design implementation DC, SOCE functional simulation NC-Verilog input patterns (stimuli) gate-level netlist power estimation PrimeTime-PX switching activity (VCD) wire load (SPEF) delay info. (SDF) power report (dynamic & leakage power) Power Estimation Flow

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