1. Impact of Guardband Reduction on Design Process Outcomes Kwangok Jeong (kjeong@vlsicad.ucsd.edu) Andrew B. Kahng (abk@cs.ucsd.edu) Kambiz Samadi (kambiz@vlsicad.ucsd.edu) University of California, San Diego

2. Outline  Motivation  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

3. Is High Yield ALWAYS Better?  High yield is a general target of IC manufacturing  But, more design effort and larger guardband are required to make a chip immune to process / environment variations 99% Yield 70% Yield Which is the better process? Foundry 1 Foundry 2 Failed chip Which is the better process?

4. How Much Benefit Comes From DFM?  Many techniques claim to reduce guardband by X%.  Gupta et. al (DAC ’04): 40% guardband reduction by adopting iso-dense variational timing analysis  Sylvester et. al (VLSITSA’99): 60% of BEOL guardband reduction  What is the value or cost of guardband?  Designer: Minimize guardband  Foundry: Maximize guardband  The impact of guardband on design process outcomes has never been quantified before. How to decide it?

5. Outline  Motivations  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

6. Why do we need guardband?  Cloud of uncertainties  Guardband should cover the uncertainties  High coverage of variations lead to high yield  Variability tolerance has been increased (cf. ITRS 2005) Defocus/Dose Variation Misalignment Temperature Variation Reliability Non-Rectangular Shapes Line-End Shortening Crosstalk IR-drop Imperfect regulators Non-Uniform CD Erosion/Dishing in CMP Electro-Migration Hot-Carrier Injection NBTI Alpha-Particle Line Edge Roughness Mask CD Error Wafer flatness Lens Aberration Flare FEOL (Front-End of Line) BEOL (Back-End of Line) Delay / Leakage Variation Capacitance/ Resistance Variation

7. Guardband vs. Design Outcomes  Delay of the setup critical path must be fast at the worst corner Increasing drive strength of cells Setup critical Hold critical  Delay of the hold critical path must be slow at the best corner Inserting delay cells Increasing Guard- band Slower @WC Faster @BC Robust Timing Opt. Increased Area Increased Runtime  Increase cost

8. Outline  Motivations  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

9. Traditional Guardband  Example of the guardband  We model the reduction of both FEOL and BEOL guardband Process VoltageTemp. FEOLBEOL NMOSPMOSCap.Res. WORSTSlow Max.Min. Low (e.g. 0.9V) High (e.g. 125  C) BESTFast Min.Max High (e.g. 1.1V) Low (e.g. -40  C)

10. FEOL Guardband: Liberty Model Scaling  Cell delay and Transition time:  M x M table  Function (Input slew, Output load)  Input capacitance:  1 x 1 table Guard Band Reduction  Reduce guardband evenly between best and worst corners pin(Z) { direction : output; max_capacitance : 0.0693; function : "(A1 A2)"; timing() { related_pin : "A1"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 (“i1, i2, i3, i4, i5, i6, i7");// Input slew index_2 (“j1, j2, j3, j4, j5, j6, j7");// Output load values(“v11, v12, v13, v14, v15, v16, v17", \ “v21, v22, v23, v24, v25, v26, v27", \ “v31, v32,...); } Value best Value worst False derating using ‘k_factor’ 0 Value best Value worst Example: 40% guardband reduction 0

11. FEOL Guardband Reduction  Goal: Entry-by-Entry BC-WC Guardband Reduction 1234 11111 22222 33333 44444 1234 24444 46666 68888 510 1234 22222 33333 44444 55555 1234 22.1 33.15 44.2 55.25 1234 23.9 35.85 47.8 59.75 Original Best Original Worst Index Matched Best New Best New Worst Inter/extra-polation w/ worst indices Move toward worst value Move toward best value Input: index-matched best/worst-case libraries and x% guardband reduction Output: guardband reduced best/worst-case libraries. for all the cells in the best/worst-case libraries: for each entry in a best-case table (value best ): (value best =value best + x/200  (value worst -value best ) for each entry in a worst-case table (value worst ): (value worst =value best - x/200  (value worst -value best ) Input: best/worst-case libraries. Output: index-matched best-case library. for all the cells in the best-case library: Find the corresponding cell in the worst case library. interpolate/extrapolate the new best-case timing table entries using the best/worst-case values. copy the slew rate index of the worst-case table on to that of the best-case table.

12. BEOL Guardband: SOCEncounter  Resistance: worst case is 1.16X greater than best  Major parameter: Temperature  Capacitance: worst case is 1.11X greater than best  Major parameter: Process Capacitance Comparison Resistance Comparison Worst = Best * 1.16 Worst = Best * 1.11 * Using OSTRICH from CADENCE Best (-40  C, 1.1V) Worst (125  C, 0.9V) Best (-40  C, 1.1V) Worst (125  C, 0.9V)

13. BEOL Guardband: Star-RCXT  Resistance: worst case is 1.17X greater than best  Major parameter: Temperature  Capacitance: worst case is 1.13X greater than best  Major parameter: Process Capacitance Comparison Resistance Comparison Worst = Best * 1.17 Worst = Best * 1.13 * Using Star-RCXT from SYNOPSYS Best (-40  C, 1.1V) Worst (125  C, 0.9V) Best (-40  C, 1.1V) Worst (125  C, 0.9V)

14. BEOL Guardband Reduction Best STAR-RCXTBEST SOCE Resistance 1 + (1.13 - 1)  (x / 200) 1 + (1.11 - 1)  (x / 200) Capacitance 1 + (1.17 - 1)  (x / 200) 1 + (1.16 - 1)  (x / 200) Worst STAR-RCXTWorst SOCE Resistance 1 - (1 - 1 / 1.13)  (x / 200) 1 + (1.11 - 1)  (x/200) Capacitance 1 - (1 – 1 / 1.17)  (x / 200) 1 + (1.16 - 1)  (x / 200)

15. Outline  Motivations  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

16. Design Flow Synthesis Scan Insertion Floorplan Placement Timing Optimization CTS Timing Optimization Routing Timing Optimization Setup? Signoff Setup? Setup Hold No Yes No Yes No Yes No Yes Cadence RTL Compiler Synopsys DFT Compiler Cadence SOC Encounter Synopsys STAR-RCXT, PrimeTime Cadence SOC Encounter

17. Testcases and Figures of Merit  Testcases  Metrics  Quality of Results  Area, # Instances, Wirelength, etc.  Design Cycle  Runtime, # violations, TNS, WNS, etc. CategoryItems DesignJpeg, Aes, 5xJpeg Guardband Reduction0%, 10%, 20%, 30%, 40%, 50% Technology90nm, 65nm Timing ModeFunction, Scan Timing CheckWorst/Best, Setup/Hold

18. Outline  Motivations  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

19. BEOL Guardband vs. FEOL Guardband (1)  FEOL Guardband is much larger than BEOL ’ s  FEOL: Worst Case Delay ~ 2 x Best Case Delay  BEOL: Worst Cap. ~ (1.11~1.13) x Best Cap. Value best Value worst Example: 50% guardband reduction on FEOL Worst case delay will be reduced by about 25% 0 100% 200% Value best Value worst Example: 50% guardband reduction on BEOL Worst case capacitance will be reduced by less than 2% 0 100% 106%

20. Impact of Guardband Reduction  FEOL  Reducing guardband greatly affects the stage delay and the timing gap between best and worst  BEOL  Reducing guardband would not affect timing much  From these observations, we can conclude FEOL will have more impacts on design outcomes. Case GB reduction Timing corner Total path delay (ns) Average Stage delay (ns) -0% Worst3.5200.147 Best1.4350.060 FEOL 10% Worst3.4060.142 Best1.5250.064 40% Worst3.0690.128 Best1.8130.076 50% Worst2.9600.123 Best1.9100.080 BEOL 10% Worst3.5150.146 Best1.4370.060 40% Worst3.5020.146 Best1.4430.060 50% Worst3.4970.146 Best1.4450.060 FEOL + BEOL 10% Worst3.4100.142 Best1.5230.063 40% Worst3.0850.129 Best1.8040.075 50% Worst2.9790.124 Best1.8990.079

21. Impact on Quality of Results (1): Area  40% of GB Reduction AREAFEOLBEOL FEOL+ BEOL Average Reduction 13 %2 %13 % Maximum Reduction 17 %6 %18 % FEOL only BEOL only FEOL+BEOL

22. Impact on Quality of Results (2): Wirelength  40% of GB Reduction WirelengthFEOLBEOL FEOL+ BEOL Average Reduction 12 %2 %12 % Maximum Reduction 18 %7 %21 % FEOL only BEOL only FEOL+BEOL

23. Impact on Design Cycle Time  Total design cycle time = f(runtime, iteration)  Iteration depends on the timing characteristics  # Violations  How many paths designer should concern  Total negative slack (TNS)  How much effort of timing optimization will be required  Worst negative slack (WNS)  Feasibility of timing convergence

24. Impact on Design Cycle Time (1): Runtime  40% of GB Reduction RuntimeFEOLBEOL FEOL+ BEOL Average Reduction 28 %2 %28 % Maximum Reduction 44 %15 %41 % FEOL only BEOL only FEOL+BEOL

25. Impact on Design Cycle Time (2): Violations  40% of GB Reduction Reduction of T.V. FEOLBEOL FEOL+ BEOL SetupHoldSetupHoldSetupHold # Violation 100 % 91 % 6 %0 % 100 % 90% WNS 100 % 77 % 10 % -2 % 100 % 76 % TNS 100 % 99 % 22 % 0 % 100 % 99 % (90nm Jpeg case) FEOL only (90nm jpeg) BEOL only (90nm jpeg) FEOL+BEOL (90nm jpeg)

26. Outline  Motivations  Background  Model Guardband Reduction  Design Flow & Test Cases  Experimental Results  Discussion: Impact on Yield  Conclusion

27. Impact on Random Defect Yield  Overall yield is defined by  Random Defect Yield  Strong function of die area (A) Binomial Probabilistic Distribution Function for good die

28. Impact on Parametric Yield  Parametric Yield vs. Guardband  Y s can be estimated by considering normal distribution with best case and worst case being set at -3σ and +3σ  For x% of guardband reduction, Y s is defined as,  For 0% guardband reduction: Ys=0.9973  For 40% guardband reduction: Ys=0.9281 about 7% yield loss

29. Impact on Yield: Scenario 1  Scenario1: Parametric yield is constant  Adopting manufacturing-aware techniques (i.e., iso- dense timing analysis, better process equipments, etc.)  foundries can reduce design guardband  40% guardband reduction results in 10% increase in total number of good dies %RGB Original die area (cm^2) logic area (cm^2) % logic area reduction die area after RGB (cm^2) Ys (3 sigma) YrY Gross die/wafer Good die/wafer 00.8500.4801.0000.850 0.997 0.8440.841759639 100.8500.4800.9360.819 0.8490.847789668 200.8500.4800.9120.808 0.8510.849801680 300.8500.4800.8950.800 0.8520.850809688 400.8500.4800.8690.787 0.8540.852823701 500.8500.4800.8500.778 0.8560.854833711 @ α=Inf., d=0.2/um^2, 300mm wafer

30. Impact on Yield: Scenario 2  Scenario 2: Guardband reduction in design process ( Actual guardband of fabrication is unchanged )  Parametric yield will decrease  Random defect yield will increase  20% guardband reduction results in 4% increase in total number of good dies per wafer

31. Conclusions  We quantify impact of guardband reduction  Typical outcome: 13%,12% and 28% reductions in standard-cell area, total wirelength and SP&R runtime metrics from 40% reduction in library model guardband  100% reduction in number of timing violations for a netlist that is synthesized with original library and extraction guardbands  this improvement can be very significant in improving timing closure and design cycle turnaround time  4% increase in the number of good dies per wafer by 20% artificial reduction from 3sigma guardband  Our results suggest that there is justification for the design, EDA and process communities to enable guardband reduction as an economic incentive for manufacturing- friendly design practices