SDW2005 - TAORMINA A NEW GENERATION OF DATA AND CONTROL INTERFACES FOR DIGITAL DETECTORS F. Bortoletto 1, M. D’Alessandro 1, E. Giro 1, R. Cosentino 2,

Slides:

Advertisements

Similar presentations

MUHAMMAD AHMED HUSSAIN

Advertisements

Provide data pathways that connect various system components.

Motherboard Components Used for Communication Among Devices

HARDWARE Rashedul Hasan..

Ali Baydoun1 Controllers (hard drive controllers).

Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University.

1 iTOP Electronics Effort LYNN WOOD PACIFIC NORTHWEST NATIONAL LABORATORY JULY 17, 2013.

256 channel data acquisition system for VISTA focal plane to readout sixteen 2k x 2k Raytheon VIRGO detectors Largest ever such system Leander H. Mehrgan.

Digital RF Stabilization System Based on MicroTCA Technology - Libera LLRF Robert Černe May 2010, RT10, Lisboa

ESODAC Study for a new ESO Detector Array Controller.

Offering the freedom to design solutions Sundance PXIe Solution.

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

Super Fast Camera System Performed by: Tokman Niv Levenbroun Guy Supervised by: Leonid Boudniak.

I/O Channels I/O devices getting more sophisticated e.g. 3D graphics cards CPU instructs I/O controller to do transfer I/O controller does entire transfer.

IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.

1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.

Detector Array Controller Based on First Light First Light PICNIC Array Mux PICNIC Array Mux Image of ESO Messenger Front Page M.Meyer June 05 NGC High.

HCAL FIT 2002 HCAL Data Concentrator Status Report Gueorgui Antchev, Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University.

ISOC Peer Review - March 2, 2004 Section GLAST Large Area Telescope ISOC Peer Review Test Bed Terry Schalk GLAST Flight Software

Manfred Meyer & IDT & ODT 15 Okt Detectors for Astronomy 2009, ESO Garching, Okt Detector Data Acquisition Hardware Designs.

ELI: Electronic Timing System (ETS) at Facility Level E L I – B L – – P R E – B.

Module I Overview of Computer Architecture and Organization.

PHY 201 (Blum) Buses Warning: some of the terminology is used inconsistently within the field.

Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf

Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January

Input/Output. Input/Output Problems Wide variety of peripherals —Delivering different amounts of data —At different speeds —In different formats All slower.

Upgrading and Expanding Portable Computers. Expansion ports are common on notebooks, which allow the user to add external devices to the computer.

About Samway Electronic SRL Founded in 2005 in Bucharest, Romania Focused on management and monitoring solutions for telecom/industrial computers Active.

Add on cards. Also known as Expansion card or interface adapter. It can be inserted into an expansion slot of a motherboard to add functionality to a.

In-Beam PET Status Report -- TPS. 2 TPS project PET monitoring prototype 2D view of the FOV coverage of the 4+4 modules Use of 4 modules vs. 4 modules.

LOGO BUS SYSTEM Members: Bui Thi Diep Nguyen Thi Ngoc Mai Vu Thi Thuy Class: 1c06.

Organization of a computer: The motherboard and its components.

Buses Warning: some of the terminology is used inconsistently within the field.

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

Computer Architecture and Organization Introduction.

AMICA Antarctic Multiband Infrared CAmera Favio Bortoletto INAF – Osservatorio Astronomico di Padova on behalf of the AMICA collaboration Telescope and.

20/10/2008A. Alici - ALICE TOF Festival1 Electronics and data acquisition of the ALICE TOF detector A.Alici University and INFN, Bologna.

Linux development on embedded PowerPC 405 Jarosław Szewiński.

The Components of a System Unit

M. Lo Vetere 1,2, S. Minutoli 1, E. Robutti 1 1 I.N.F.N Genova, via Dodecaneso, GENOVA (Italy); 2 University of GENOVA (Italy) The TOTEM T1.

1 Abstract & Main Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The focus of this project was the creation of an analyzing device.

MRF & Cosylab on timing system: integration support Joze Dedic the best people make cosylab … Head of Hardware.

11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.

Author Wayne M. Koski EVLA Monitor & Control Hardware PDR March 13, EVLA Monitor and Control Module Interface Board (MIB) Design.

CS-350 TERM PROJECT COMPUTER BUSES By : AJIT UMRANI.

Organisasi Sistem Komputer Materi VIII (Input Output)

Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.

Computer Hardware The Processing Unit.

PART 7 CPU Externals CHAPTER 7: INPUT/OUTPUT 1. Input/Output Problems Wide variety of peripherals – Delivering different amounts of data – At different.

CPU/BIOS/BUS CES Industries, Inc. Lesson 8.  Brain of the computer  It is a “Logical Child, that is brain dead”  It can only run programs, and follow.

Total Embedded Solutions SubSystems. Total Embedded Solutions SubSystems Agenda SSD Background Embedded Products –MIPS based processor products –I/O cards.

PHY 201 (Blum) Comparators and Buses. PHY 201 (Blum) What is it? A comparator is circuitry that compares two inputs A and B, determining whether the following.

Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao.

Clara Gaspar on behalf of the ECS team: CERN, Marseille, etc. October 2015 Experiment Control System & Electronics Upgrade.

S.Anvar, V.Gautard, H.Le Provost, F.Louis, K.Menager, Y.Moudden, B.Vallage, E.Zonca, on behalf of the KM3NeT consortium 1 IRFU/SEDI-CEA Saclay F

Fault Tolerant LEON 3FT Processing Fault Tolerant LEON 3FT Processing Device and Circuit Boards Sam Stratton Aeroflex Colorado Springs

Brandon Halleran.  The power supply for your personal computer gives your machine all the different voltages it needs to operate properly. It is able.

17/02/06H-RORCKIP HeidelbergTorsten Alt The new H-RORC H-RORC.

COMPASS DAQ Upgrade I.Konorov, A.Mann, S.Paul TU Munich M.Finger, V.Jary, T.Liska Technical University Prague April PANDA DAQ/FEE WS Игорь.

SEPTEMBER 8, 2015 Computer Hardware 1-1. HARDWARE TERMS CPU — Central Processing Unit RAM — Random-Access Memory  “random-access” means the CPU can read.

THE COMPUTER MOTHERBOARD AND ITS COMPONENTS Compiled By: Jishnu Pradeep.

Vladimir Zhulanov for BelleII ECL group Budker INP, Novosibirsk INSTR2014, Novosibirsk 2014/02/28 1.

System on a Programmable Chip (System on a Reprogrammable Chip)

Altera Stratix II FPGA Architecture

Read-out of High Speed S-LINK Data Via a Buffered PCI Card

The electronics system of the TOTEM T1 telescope

The digital read-out for the CSC system of the experiment TOTEM at LHC

Presentation transcript:

SDW TAORMINA A NEW GENERATION OF DATA AND CONTROL INTERFACES FOR DIGITAL DETECTORS F. Bortoletto 1, M. D’Alessandro 1, E. Giro 1, R. Cosentino 2, M. Belluso 2, A. Carbone 3, M. Gemma 3 1 INAF-Osservatorio Astronomico di Padova Italy, 2 INAF-Osservatorio Astronomico di Catania Italy, 3 SKYTECH LaSpezia Italy

SDW TAORMINA Project Main Requirements: 1.Upgrade for the precedent generation of transputer based VME/VSB boards saving compatibility with high level SW (table editors) 2. Compatibility with modern bus architecture, I.E.: PCI, CPCI, VME and modern bus-adapters (AMCC chips) 3.Use of host computer memory for data storage via PCI fast data transfers 4.Use of fast throughput, full-duplex, data & controls link between host interface and remote electronics 5.On board (host interface) generation of detector clock sequences and transmission through the fast control link

SDW TAORMINA The PCI model for the sequencer/interface board : Simplified PCI version for the sequencer/interface board PCI sequencer/interface board main functions

SDW TAORMINA Dual slots PMC piggy-back detector interface mounted on a Motorola C-PCI CPU PMC sequencer & detector Interface main functions The PMC model for the sequencer/interface board : The PMC module can be mounted in a variety of VME/C-PCI boards. It implements the same concept found on the PCI version with the presence of a large, host computer, configurable FPGA dedicated to the implementation of fast local functions on the data-flow

SDW TAORMINA Glue-Logic is embedded on a Xilinx FPGA. It provides communication with the PCI/PMC host I/F board and all the logics for the implementation of a detector controller in a scalable way The Remote Glue Logic Board : Example of Glue-Logic remote board with programmable clocks, services, telemetry and system bus implemented on a 8 layers SMD double-euro card

SDW TAORMINA System Expansion for High Number of Video Channels: A common synchronization line driven by a master PCI/PMC interface allows expansion to a distributed acquisition system. GLUE-LOGIC BOARDS