1. The electronics system of the TOTEM T1 telescope
presented by Saverio MINUTOLI
I.N.F.N. Genova – via Dodecaneso 33 – Genova (I)
T1 Telescope, Inelastic detector in the region 3.1 < |h| < 4.7
Cathode Strip Chambers,
Ar/CO2/CF4 mix
Shown half
T1 telescope
cathode plane
Read-out of anode wires and cathode strips at ± 60º
Three coordinates.
5 planes, 6 sextants each, inside CMS muon end-cap
Digital read-out chosen for both anodes and cathodes
Custom Front-End VLSI chip called VFA (CERN-TOTEM design)
Trigger implemented with groups of wires
Hits and trigger bits optically transmitted
LHC clock and fast commands compliant
Insertion of one half-arm of T1 (IP5 '–' side).

2. Cathode Front-End Card
F-E VFAT hybrid
The VFAT chip has 128 channels input
Produces Hits and Trigger information
Hits information is in the form of binary patterns
Trigger information is provided by programmable fast “ORs”
Anode Front-End Card
10 shapes driven by T1 geometry
hosts two VFAT hybrids (256 chs)
60 boards installed
11,100 channels acquired
VFAT hybrid
Basic architecture of the Read-out system
AFEC
Cathode Front-End Card
hosts one VFAT hybrid (128 chs)
160 boards installed
~16,000 channels acquired
CFEC
Read Out Control board
36 boards installed
Manages up to two CSC chambers
Collects hits data and trigger bits
Hosts 3 optical transmission link, Ethernet 8B/10B
Includes the trigger bits synchronization circuitry
Embedded slow control link based on CMS-CCU device
Implements Redundant Skip Fault Architecture
Hosts custom FPGA based spy mezzanine
ROC