1. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 1 Read-out of High Speed S-LINK Data Via a Buffered PCI Card A. Guirao Talk for the 4 th PCaPAC International Workshop CERN- EP division, ED Electronics group A.Guirao, F. Bal, M.E. Castro, H.Müller, K. Wyllie, CERN S.Jolly, Imperial College London F.Ballester, UPV

2. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 2 Contents Introduction to project requirements Minimizing a previous test system What the PC architecture and PCI offer The concept of the new solution Building the real system S-LINK Front-end electronics PCI hardware readout controller Software control interface Performance Conclusions and outlook

3. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 3 Project Requirements Laboratory test system for LHCb RICH Pixel Chips Test system on-line within 3 months 40MHz clock rate 1MHz event-rate, 32 DWORDs burst per event Inexpensive Flexible functionality Portable and handy– different applications Chip characterisation Wafer testing Module (Photodetector) testing Testbeams

4. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 4 READOUT CTRLER (CPU) READOUT CARD I/O Minimizing a PIXEL chip test system Solution for the previous version of the pixel chip (10MHz test system) READOUT CARD I/O BACKPLANE BUS CRATE DETECTOR (PIXEL CHIP) DAQ computer New solution PCI BUS CTLER I/O CTLER I/O DAQ computer

5. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 5 The PC architecture and PCI Advantages: CPUs and many hardware resources available Most common and familiar bus architecture FPGA support Any conventional OS works with the PCI Low cost Partitionable (several controllers per bus) PCI 32b@33MHz, 64b@66MHz, cPCI available Drawbacks:  Limited space for electronics  Limited power

6. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 6 Concept of the new solution PCI READOUT CONTROLLER FPGA I/Os Custom protocol APPLICATION LAYER HAL SYSTEM HARDWARE HOST BRIDGE ON-BOARD MEMORY SYSTEM MEMORY CPU DLL/module HARDWARESOFTWARE

7. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 7 Building a real system 1 2

8. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 8 S-LINK Front-End electronics Single mode (32 dwords for LHCb) or multievent readout mode (up to 16 events per trigger) Adaptation of S-LINK bus width for LVDS serializers

9. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 9 PCI Readout Controller The FLIC card Standard PCI card  small, familiar Easy to use (Plug&Play) General Purpose solution Mezzanine cards interchangeable Custom HW interface (FPGA, HDL) Low cost Large data buffer  local memory becomes system memory FPGA LOGIC

10. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 10 Readout Software LabView Analysis and Interface Existing analysis software for the chip Interface with commercial cards (JTAG controller) Need of developing a Windows TM driver for the FLIC Existing support for Linux

11. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 11 Performance DATA SOURCE LHCb pixel mode 40MHz clock 32 dwords burst SLINK 32b@40MHz SLINK FLIC 32b@33MHz 132MB/s payload FLIC input 64b@16MHz 132MB/s SDRAM 64MB MEMORY BANKS HARDWARE SOFTWARE PCI 32b@33MHz LabView interface 3MB/s REAL-TIME OFFLINE Jungo driver FLIC specific DLL

12. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 12 Conclusions and Future Conclusions A test system has been built based on PCI controller 40MHz performance reached More systems have been reproduced in short time Low cost per system Works under LabView Logically compatible with the previous test system Easy maintenance and upgrading Future possibilities Scalability: several readout controllers per PC Higher speed in the software domain (DMA engines) More complex controllers may fit in larger FPGAs

13. Guirao - Frascati 2002Read-out of high-speed S-LINK data via a buffered PCI card 13 Thanks!