STaRBoard Jamal Rorie 5/09/06

Data Collection TDC Leading Edge Lo Level Discriminator Mean Timer 1:3 Splitter ADC Leading Edge Hi Level Discriminator Leading Edge Lo Level Discriminator TDC 1:3 Splitter Leading Edge Hi Level Discriminator ADC PMT

Timing Scheme Hi level - event trigger Lo level - higher time resolution

Timing Scheme (cont.) Timing Scheme (cont.) Current System: stretch interval between TOFFEE “T” pulse rising edge and rising edge of a reference signal. Measure stretched time. New System: use HPTDC in high resolution mode to time the rising edge from the TOFFEE “T” pulse. –4 TDC channels take measurements, result is interpolated. –More info on high resolution mode in HPTDC Manual on pp 7-8.

Q Measurement Current System: send directly into LeCroy 1877S, convert to time New System: send to ADC block on STaR –Shaper –LABRADOR3

Readout Scheme Event trigger received by STaR Logic request to HPTDC HPTDC polls for “hit” around requested time HPTDC sends data, Logic queries LAB3 No HPTDC data, Logic doesn’t query LAB3 LAB3 sends data COPPER I/O carries data downstream Hit No Hit

COPPER COmmon Pipelined Platform for Electronics Readout One standardized card can control up to 4 boards

STaR Layout HPTDC LAB3 XC3S2000 COPPER 16 CLK

The STaR Board

ADC Block LABRADOR3 –12 bit data readout Shaper to elongate signal –Originally 3 GSPS –Now MSPS

Readout LAB3 header format under discussion

Testing Shaper Test –Elongation good –Standard delay confirming

Tasks Currently –Firmware development Ahead –Software development –Firmware testing –Finalization –KEK observations (mid-July)

Online Documentation –Schematics –Updates –Code –Datasheet