1. Performance of the AMT-3 Based TDC System at Belle S.Y.Suzuki, T.Higuchi, Y.Arai, K.Tauchi, M.Nakao, R.Itoh (KEK) H.Nakayama (University of Tokyo)

2. Belle experiment at KEKB Designed luminosity Study of CP violation in B-meson decays from Y(4S) The Belle detector consists of 7 sub-detectors. L1 trigger – 500Hz(average) Data size – 40kB/ev Achieved 160% of the designed lumionsity.

3. Schematic view of DAQ system Trigger, Sequence Controll SEQ ACC CDC TOF ECL KLM EFC TRG SVD Readout Subsystems Reconstruction Farm Online farm FASTBUS VME PC Multihit TDC Using Q-to-T + multi-hit TDC technique, most of detectors are read out by the same FASTBUS TDC system. Except deadtime, FASTBUS is excellent.

4. Present FASTBUS DAQ system TDC – LeCroy 1877S FASTBUS –High channel density : 96ch per board –Fine resolution : 16bit x 500ps LSB, 32μsec window –Q-to-T : Multi-hit up to 16 edges per channel Unified DAQ system : easy to maintain. Except deadtime –No pipeline : trigger and busy hanshake in delay + common-stop

5. Deadtime fraction VETO for 10Hz continuous injection So we developed new readout system. Deadtime fraction (%) Deadtime is proportional to the product of the trigger rate and the data size. This deadtime comes from FASTBUS TDC. Luminosity increase makes the higher trigger rate and larger data size. Trigger (Hz)

6. Pipelined readout system Smooth upgrade path Unified readout system New DAQ concept

7. Design of new readout system Digitizer –Pipelined digitization Readout FIFO –Event buffers for asynchronous readout Online processor –Data size reduction –Data transmission over TCP/IP Digitizer Readout FIFO Online Processor Signals from detector Everything on a single board

8. PMC CPU local bus PCI bus from detector Network IF Trigger Module Digitizer Bridge PMC modules FIFO to event builder Schematic view of “COPPER” Readout FIFO Trigger Busy Trigger and busy handshake for the smooth upgrade. COPPER co-exists with present FASTBUS TDC readout.

9. AMT-3 Replacement of FASTBUS TDC with pipelined TDC AMT-3 based TDC is implemented in the digitizer card of the COPPER. AMT-3 chip originally developed for ATLAS –Pipeline TDC –Multiple buffers allow asynchronous readout Channel buffer L1 FIFO Readout FIFO –24ch LVDS input/chip –780ps LSB x 17bit, 102.4μsec window –250ps Time resolution (RMS) Similar spec to the FASTBUS TDC, suitable for the replacement.

10. The COPPER TDC Add-on module for COPPER –2 AMT-3 chips per module –48 ECL inputs (ECL-to-LVDS converter) COPPER TDC –2 add-on modules per COPPER –96 inputs in total –Connector shapes and signal level are compatible with LeCroy FASTBUS TDC’s.

11. The COPPER TDC

12. History of COPPER study Since September 2005, first 6-module test setup commissioned in Extreme Forward Calorimeter. Since September 2006, 16-module setup commissioned for the Central Drift Chamber readout. Performance was compared with the FASTBUS system.

13. 16-module setup Signals are daisy-chained to FASTBUS via COPPER. … … … … Central Drift Chamber ShaperQT Signals are digitized simultaneously by FASTBUS and COPPER for the consistency check.

14. Data consistency FASTBUS time (ns) COPPER time (ns)

15. Linearity / Resolution It is consistent with the specification of AMT-3 itself, Time resolution ~ 250ps (RMS) RMS is 0.61LSB Difference from the expected value (LSB) AMT-3 time (ns) Diff from the expected value (LSB) # of events

16. Deadtime improvement Offset = 25usec Offset = 0.72us 29.5us 2.8us # of hits/TDC Deadtime (us) Nominal data size Deadtime is < ~ 1/10

17. Summary Higher trigger rate and larger data size are expected in near future. We developed a new pipelined TDC to reduce the deadtime. 1/10 shorter deadtime is achieved. (29.5us -> 2.8us) It was proven to have sufficient performance to supersede current FASTBUS readout system. –Compatible with the FASTBUS TDC